Datasheet > CYT2CL7BAAQ0AZSGS

CYT2CL7BAAQ0AZSGS

更新时间： 2024-03-03 10:10:13

品牌	Logo	应用领域
英飞凌 - INFINEON		/
页数	文件大小	规格书
179页	3416K
描述
TRAVEO? T2G CYT2CL

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CYT2CL

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

General description

CYT2CL is a family of TRAVEO™ T2G microcontrollers targeted at automotive systems such as cluster entry units.

CYT2CL has an Arm® Cortex®-M4F CPU for primary processing, and an Arm® Cortex®-M0+ CPU for peripheral and

security processing. These devices contain embedded peripherals supporting controller area network with

flexible data rate (CAN FD), local interconnect network (LIN), clock extension peripheral interface (CXPI), LCD

controller. TRAVEO™ T2G devices are manufactured on an advanced 40-nm process. CYT2CL incorporates

Infineon's low-power flash memory, multiple high-performance analog and digital peripherals, and enables the

creation of a secure computing platform.

Features

• Dual CPU subsystem

- 160-MHz (max) 32-bit Arm® Cortex®-M4F CPU with

• Single-cycle multiply

• Single-precision floating point unit (FPU)

• Memory protection unit (MPU)

- 100-MHz (max) 32-bit Arm® Cortex®-M0+ CPU with

• Single-cycle multiply

• Memory protection unit

- Inter-processor communication in hardware

- Three DMA controllers

• Peripheral DMA controller #0 (P-DMA0) with 76 channels

• Peripheral DMA controller #1 (P-DMA1) with 84 channels

• Memory DMA controller #0 (M-DMA0) with 4 channels

• Integrated memories

- Up to 4160 KB of code-flash with an additional 128 KB of work-flash

• Read-While-Write (RWW) allows updating the code-flash/work-flash while executing code from it

• Single- and dual-bank modes (specifically for Firmware update Over The Air [FOTA])

• Flash programming through SWD/JTAG interface

- Up to 512 KB of SRAM with selectable retention granularity

• Crypto engine^[1]

- Supports Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM)

- Secure boot and authentication

• Using digital signature verification

• Using fast secure boot

- AES: 128-bit blocks, 128-/192-/256-bit keys

- 3DES: 64-bit blocks, 64-bit key

- Vector unit supporting asymmetric key cryptography such as Rivest-Shamir-Adleman (RSA) and Elliptic Curve

(ECC)

- SHA-1/2/3: SHA-512, SHA-256, SHA-160 with variable length input data

- CRC: supports CCITT CRC16 and IEEE-802.3 CRC32

- True random number generator (TRNG) and pseudo random number generator (PRNG)

- Galois/Counter Mode (GCM)

Note

1. Crypto engine features are available on select MPNs.

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 1

002-32508 Rev. *H

2023-05-19

12 3 4 5 6 7...179

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