Datasheet > CYS25G0101DX_07

CYS25G0101DX_07

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
17页	279K
描述
SONET OC-48 Transceiver

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数据手册

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CYS25G0101DX_07 数据手册

CYS25G0101DX

Pin Configuration

The pin configuration for 120-pin Thin Quad Flatpack follows. ^{[1, 2]}

Figure 2. 120-Pin Thin Quad Flatpack Pin Configuration

Top View

LFI

RESET

VCCQ

VSSQ

DIAGLOOP

LINELOOP

LOOPA

REFCLK+

REFCLK–

VSSN

LOOPTIME

PWRDN

VCCN

VSSN

VCCN

LOCKREF

RXD[0]

RXD[1]

RXD[2]

RXD[3]

VSSN

VDDQ

RXD[4]

RXD[5]

RXD[6]

RXD[7]

VSSN

VDDQ

RXCLK

VSSN

VDDQ

VSSN

TXCLKO

VSSN

CYS25G0101DX

VDDQ

TXD[0]

TXD[1]

TXD[2]

TXD[3]

VCCQ

VSSQ

VCCN

VSSN

TXD[4]

TXD[5]

TXD[6]

TXD[7]

TXD[8]

TXD[9]

TXD[10]

TXD[11]

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Notes

1. No connect (NC) pins are left unconnected or floating. Connecting any of these pins to the positive or negative power supply causes improper operation or failure of

the device.

2. Pins 113 and 119 are either no connect or VSSQ. Use VSSQ for compatibility with next generation of OC-48 SERDES devices. Pin 116 are either no connect or VCCQ.

Use VCCQ for compatibility with next generation of OC-48 SERDES devices.

Document Number: 38-02009 Rev. *K

Page 4 of 17

1 2 345 6 7...17

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