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CYPD5225-96BZXI PDF预览

CYPD5225-96BZXI

更新时间: 2024-10-28 21:17:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 外围集成电路
页数 文件大小 规格书
38页 742K
描述
Microprocessor Circuit, CMOS, PBGA96, BGA-96

CYPD5225-96BZXI 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:VFBGA,Reach Compliance Code:compliant
HTS代码:8542.31.00.01风险等级:2.18
JESD-30 代码:S-PBGA-B96长度:6 mm
端子数量:96最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:VFBGA封装形状:SQUARE
封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH座面最大高度:1 mm
最大供电电压:5.5 V最小供电电压:2.7 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:BALL端子节距:0.5 mm
端子位置:BOTTOM宽度:6 mm
uPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUITBase Number Matches:1

CYPD5225-96BZXI 数据手册

 浏览型号CYPD5225-96BZXI的Datasheet PDF文件第2页浏览型号CYPD5225-96BZXI的Datasheet PDF文件第3页浏览型号CYPD5225-96BZXI的Datasheet PDF文件第4页浏览型号CYPD5225-96BZXI的Datasheet PDF文件第5页浏览型号CYPD5225-96BZXI的Datasheet PDF文件第6页浏览型号CYPD5225-96BZXI的Datasheet PDF文件第7页 
PRELIMINARY  
EZ-PD™ CCG5  
USB Type-C Port Controller  
General Description  
EZ-PD™ CCG5 is a dual USB Type-C controller that complies with the latest USB Type-C and PD standards. EZ-PD CCG5 provides  
a complete dual USB Type-C and USB-Power Delivery port control solution for PCs, notebook, and dock. It can also be used in dual  
role and downstream facing port applications. EZ-PD CCG5 uses Cypress’s proprietary M0S8 technology with a 32-bit, 48-MHz ARM®  
Cortex®-M0 processor with 128 KB flash and integrates two complete Type-C Transceivers including the Type-C termination resistors  
RP and RD. CCG5 also integrates high voltage regulator. CCG5 is available in 40-QFN (1 port) and 96-BGA (2 ports).  
Integrated Digital Blocks  
Up to two integrated timers and counters to meet response  
times required by the USB-PD protocol  
Applications  
PCs, Notebook, and Dock  
Four run-time serial communication blocks (SCBs) with  
Features  
reconfigurable I2C, SPI, or UART functionality  
Type-C and USB-PD Support  
Integrated USB Power Delivery 3.0 support  
Clocks and Oscillators  
Integrated oscillator eliminating the need for external clock  
Two integrated USB-PD Type-C ports  
Integrated UFP[1] (RD) and current sources for DFP[2] (RP) on  
both Type-C ports  
Low-Power Operation  
2.7-V to 21.5-V operation  
Independent supply voltage pin for GPIO that allows 1.71-V to  
5.5-V signaling on the I/Os  
Integrated dead battery termination for DRP (Power  
Source/Sink) applications  
Integrated VCONN FETs to power EMCA cables  
Integrated fast role swap and extended data messaging  
Integrated High Voltage LDO, operational up to 21.5V  
Integrated 2x USB Analog Mux  
System-Level ESD on CC, D+/-, and SBU Pins  
±8-kVContactDischargeand±15-kVAirGapDischargebased  
on IEC61000-4-2 level 4C  
Hot Swappable I/Os  
Port 1 I2C pins and CC1, CC2 pins are hot-swappable  
Integrated 2x SBU Analog Mux  
Integrated 2x USB Charger detect blocks (BC v1.2, Apple  
Charging)  
Packages  
6.0 mm 6.0 mm, 0.6 mm, 40-pin QFN,   
6.0 mm 6.0 mm, 1.0 mm, 96-ball BGA  
Integrated OVP and OCP protection on the VBUS  
Integrated OCP protection on the VCONN  
Integrated high voltage protection on CC and SBU pins to  
protectagainstaccidentalshortstotheVBUSpinontheType-C  
connector  
Supports industrial temperature range (–40 °C to +85 °C)  
Integrated Current sense amplifier that supports high-side  
current sensing  
Integrated gate drivers for external VBUS PFET control on  
Type-C Ports  
Supports high-voltage tolerant PFET-controlled GPIOs  
32-bit MCU Subsystem  
48-MHz ARM Cortex-M0 CPU  
128-KB Flash  
12-KB SRAM  
Notes  
1. UFP refers to Power Sink.  
2. DFP refers to Power Source.  
Errata: For information on silicon errata, see “Errata” on page 36. Details include trigger conditions, devices affected, and proposed workaround.  
Cypress Semiconductor Corporation  
Document Number: 002-17682 Rev. *B  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised June 3, 2017  

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