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CYIL1SM4000AA-GDC

更新时间： 2024-01-15 08:08:28

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		传感器换能器图像传感器时钟
页数	文件大小	规格书
38页	1105K
描述
4M Pixel CMOS Image Sensor

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CYIL1SM4000AA-GDC 技术参数

生命周期：	Obsolete	Reach Compliance Code：	unknown
风险等级：	5.26	其他特性：	ELECTRONIC SHUTTER
阵列类型：	FULL FRAME	主体宽度：	42 mm
主体高度：	3.25 mm	主体长度或直径：	42 mm
动态范围：	66 dB	帧速率：	15 fps
水平像素：	2048	外壳：	CERAMIC
主时钟：	33 MHz	安装特点：	SURFACE MOUNT
最大工作电流：	50 mA	最高工作温度：	60 °C
最低工作温度：		输出接口类型：	3-WIRE INTERFACE
输出范围：	-0.50-3.80V	输出类型：	DIGITAL VOLTAGE
封装形状/形式：	SQUARE	像素大小：	12X12 µm
灵敏度（V / lx.s）：	11.61 V/lx.s	传感器/换能器类型：	IMAGE SENSOR,CMOS
最大供电电压：	2.75 V	最小供电电压：	2.25 V
表面贴装：	YES	端接类型：	SOLDER
垂直像素：	2048	Base Number Matches：	1

CYIL1SM4000AA-GDC 数据手册

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LUPA-4000

The output voltage of Out1 will be between 1.3V (dark level)

and 0.3V (white level) and depends on process variations and

voltage supply settings. The output voltage of Out2 is

determined by the DAC.

ADC should be tied externally to the outputs of the output

amplifiers.

One ADC will sample the even columns and the other one will

sample the odd columns. Although the input range of the ADC

is between 1V and 2V and the output range of the analog

signal is only between 0.3V and 1.3V, the analog output and

digital input may be tied to each other directly. This is possible

because there is an on chip level-shifter located in front of the

ADC to lift up the analog signal to the ADC range.

Pixel array drivers

We have foreseen on this image sensor on chip drivers for the

pixel array signals. Not only the driving on system level is easy

and flexible, also the maximum currents applied to the sensor

are controlled on chip. This means that the charging on sensor

level is fixed and that the sensor cannot be overdriven from

externally. In the paragraph on the timing, the operation of the

on-chip drivers is explained more in detail.

Table 6. ADC specifications

Parameter

Input range

Specification

1 - 2V (*)

Column amplifiers

Quantization

10 Bits

The column amplifiers are designed for minimum power dissi-

pation and minimum loss of signal for this reason multiple

biasing signals are needed.

Nominal data rate

33 Msamples/s

DNL (linear conversion mode) Typ. < 0.4 LSB RMS

The column amplifiers also have the "voltage-averaging"

feature integrated. In case of voltage averaging mode, the

voltage average between 2 columns is taken and read out. In

this mode only 2:1 pixels have to be read out.

INL (linear conversion mode)

Input capacitance

Typ. < 3.5 LSB

< 2 pF

Power dissipation @ 33 MHz

Conversion law

50 mW

To achieve the voltage-averaging mode, an additional external

digital signal called "voltage-averaging" is required in

combination with a bit from the SPI.

Linear/Gamma-corrected

ADC timing

Analog to Digital Converter

The ADC converts the pixel data on the falling edge of the

ADC_CLOCK but it takes 2 clock cycles before this pixel data

is at the output of the ADC. This pipeline delay is shown in

Figure .

The LUPA4000 has a two 10 bit flash analog digital converters

running nominally at 33 Msamples/s. The ADC's are

electrically separated from the image sensor. The inputs of the

Figure 6. ADC timing

Note

4. The internal ADC range will be typ. 50 mV lower then the external applied ADC_VHIGH and ADC_VLOW voltages due to voltage drops over parasitic internal

resistors in the ADC.

Document Number: 38-05712 Rev. *B

Page 10 of 38

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