CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
then the SEM pin must be asserted instead of the CE pin, and
OE must also be asserted.
The inputs will be 1.8V/2.5V LVCMOS or 3.0V LVTTL,
depending on the core voltage supply (VCC). Refer to Table 3
for Input Read Register operation.
Interrupts
IRR is not available in the CYDC256B16 and CYDC128B08,
The upper two memory locations may be used for message
passing. The highest memory location (FFF for the
CYDC064B16, 1FFF for the CYDC128B16 and CYDC064B08,
3FFF for the CYDC256B16 and CYDC128B08) is the mailbox
for the right port and the second-highest memory location (FFE
for the CYDC064B16, 1FFE for the CYDC128B16 and
CYDC064B08, 3FFE for the CYDC256B16 and CYDC128B08)
is the mailbox for the left port. When one port writes to the
other port’s mailbox, an interrupt is generated to the owner.
The interrupt is reset when the owner reads the contents of the
mailbox. The message is user-defined.
as the IRR pins are used as extra address pins A13L and A13R
.
Output Drive Register
The Output Drive Register (ODR) determines the state of up
to five external binary state devices by providing a path to VSS
for the external circuit. These outputs are Open Drain.
The five external devices can operate at different voltages
(1.5V ≤ VDDIO ≤ 3.5V) but the combined current cannot exceed
40 mA (8 mA max for each external device). The status of the
ODR bits are set using standard write accesses from either
port to address x0001 with a “1” corresponding to on and “0”
corresponding to off.
Each port can read the other port’s mailbox without resetting
the interrupt. The active state of the busy signal (to a port)
prevents the port from setting the interrupt to the winning port.
Also, an active busy to a port prevents that port from reading
its own mailbox and, thus, resetting the interrupt to it.
The status of the ODR bits can be read with a standard read
access to address x0001. When SFEN = VIL, the ODR is active
and address x0001 is not available for memory accesses.
When SFEN = VIH, the ODR is inactive and address x0001 can
be used for standard accesses.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin. On power up, an initialization program should be run
and the interrupts for both ports must be read to reset them.
During reads and writes to ODR DQ<4:0> are valid and
DQ<15:5> are don’t care. Refer to Table 4 for Output Drive
Register operation.
The operation of the interrupts and their interaction with Busy
are summarized in Table 2.
Semaphore Operation
The
CYDC256B16,
CYDC128B16,
CYDC064B16,
Busy
CYDC128B08, CYDC064B08 provide eight semaphore
latches, which are separate from the dual-port memory
locations. Semaphores are used to reserve resources that are
shared between the two ports. The state of the semaphore
indicates that a resource is in use. For example, if the left port
wants to request a given resource, it sets a latch by writing a
zero to a semaphore location. The left port then verifies its
success in setting the latch by reading it. After writing to the
semaphore, SEM or OE must be deasserted for tSOP before
attempting to read the semaphore. The semaphore value will
be available tSWRD + tDOE after the rising edge of the
semaphore write. If the left port was successful (reads a zero),
it assumes control of the shared resource, otherwise (reads a
one) it assumes the right port has control and continues to poll
the semaphore. When the right side has relinquished control
of the semaphore (by writing a one), the left side will succeed
in gaining control of the semaphore. If the left side no longer
requires the semaphore, a one is written to cancel its request.
The
CYDC256B16,
CYDC128B16,
CYDC064B16,
CYDC128B08, CYDC064B08 provide on-chip arbitration to
resolve simultaneous memory location access (contention). If
both ports’ CEs are asserted and an address match occurs
within tPS of each other, the busy logic will determine which
port has access. If tPS is violated, one port will definitely gain
permission to the location, but it is not predictable which port
will get that permission. BUSY will be asserted tBLA after an
address match or tBLC after CE is taken LOW.
Master/Slave
A M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the
slave. This will allow the device to interface to a master device
with no external components. Writing to slave devices must be
delayed until after the BUSY input has settled (tBLC or tBLA),
otherwise, the slave chip may begin a write cycle during a
contention situation. When tied HIGH, the M/S pin allows the
device to be used as a master and, therefore, the BUSY line
is an output. BUSY can then be used to send the arbitration
outcome to a slave.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same
manner as a normal memory access. When writing or reading
a semaphore, the other address pins have no effect.
Input Read Register
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one will
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes
control by writing a one to the semaphore, the semaphore will
be set to one for both sides. However, if the right port had
requested the semaphore (written a zero) while the left port
had control, the right port would immediately own the
semaphore as soon as the left port released it. Table 5 shows
sample semaphore operations.
The Input Read Register (IRR) captures the status of two
external input devices that are connected to the Input Read
pins.
The contents of the IRR read from address x0000 from either
port. During reads from the IRR, DQ0 and DQ1 are valid bits
and DQ<15:2> are don’t care. Writes to address x0000 are not
allowed from either port.
Address x0000 is not available for standard memory accesses
when SFEN = VIL. When SFEN = VIH, address x0000 is
available for memory accesses.
Document #: 001-01638 Rev. *E
Page 6 of 26
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