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CYD36S72V18-133BBI PDF预览

CYD36S72V18-133BBI

更新时间: 2023-08-15 00:00:00
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
48页 938K
描述
Dual-Port SRAM, 512KX72, 4.5ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-484

CYD36S72V18-133BBI 数据手册

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PRELIMINARY  
FullFlex  
FTSEL  
CQEN  
PORTSTD[1:0]  
FTSEL  
L
R
CQEN  
L
R
CONFIG Block  
CONFIG Block  
PORTSTD[1:0]  
L
R
DQ [71:0]  
R
DQ[71:0]  
L
BE [7:0]  
R
BE [7:0]  
L
CE0  
R
CE0  
L
IO  
Control  
IO  
Control  
CE1  
R
CE1  
L
OE  
R
OE  
L
R/W  
R
R/W  
L
CQ1  
CQ1  
L
CQ1  
R
R
R
CQ1  
L
CQ0  
CQ0  
CQ0  
L
CQ0  
L
R
Dual Ported Array  
VC_SEL  
BUSY  
Collision Detection Logic  
BUSY  
L
R
A [20:0]  
A [20:0]  
L
L
R
R
CNT/MSK  
CNT/MSK  
ADS  
ADS  
R
L
CNTEN  
CNTEN  
R
L
Address &  
Counter Logic  
Address &  
Counter Logic  
CNTRST  
CNTRST  
L
R
RET  
L
RET  
R
CNTINT  
L
CNTINT  
R
C
L
C
R
WRP  
L
WRP  
R
TRST  
TMS  
TDI  
Mailboxes  
INT  
INT  
R
L
JTAG  
TDO  
TCK  
ZQ0  
ZQ0  
L
R
ZQ1  
ZQ1  
L
R
RESET  
LOGIC  
MRST  
READY  
READY  
LowSPD  
L
L
R
LowSPD  
R
Figure 1. FullFlex72 18-Mbit (CYD18S72V18) Block Diagram[1, 2, 3]  
Notes:  
1. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and the CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18,  
and the CYD09S18V18 devices have 19 address bits. The CYD18S72V18, CYD09S36V18, and the CYD04S18V18 devices have 18 address bits. The  
CYD09S72V18 and the CYD04S36V18 devices have 17 address bits. The CYD04S72V18 has 16 address bits.  
2. The FullFlex72 family of devices has 72 data lines. The FullFlex36 family of devices has 36 data lines. The FullFlex18 family of devices has 18 data lines.  
3. The FullFlex72 family of devices has eight byte enables. The FullFlex36 family of devices has four byte enables. The FullFlex18 family of devices has two byte  
enables.  
Document #: 38-06082 Rev. *C  
Page 2 of 48  

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