Datasheet > CYD36S72V18-133BBI

CYD36S72V18-133BBI

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
48页	938K
描述
Dual-Port SRAM, 512KX72, 4.5ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-484

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PRELIMINARY

FullFlex

Document History Page

Document Title: FullFlex™ Synchronous SDR Dual-Port SRAM

Document Number: 38-06082

Issue

Date

302411 See ECN

Orig. of

Change

YDT

REV.

ECN NO.

Description of Change

New data sheet

334036 See ECN

YDT

Corrected typo on page 1

Reproduced PDF file to fix formatting errors

395800 See ECN

SPN

Added statement about no echo clocks for flow-through mode

Updated electrical characteristics

Added note 16 and 17 (1.5V timing)

Added note 33 (timing for x18 devices)

Updated input edge rate (note 34)

Updated table 5 on deterministic access control logic

Added description of busy readback in deterministic access control section

Changed dummy write descriptions

Updated ZQ pins connection details

Updated note 24, B0 to BE0

Added power supply requirements to MRST and VC_SEL

Added note 4 (VIM disable)

Updated supply voltage to ground potential to 4.1V

Updated parameters on table 15

Updated and added parameters to table 16

Updated x72 pinout to SDR only pinout

Updated 484 PBGA pin diagram

Updated the pin definition of MRST

Updated the pin definition of VC_SEL

Updated READY description to include Wired OR note

Updated master reset to include wired OR note for READY

Updated minimum V_OHvalue for the 1.8V LVCMOS configuration

Updated electrical characteristics to include I_OHand I_OLvalues

Updated electrical characteristics to include READY

Added I_IX3

Updated maximum input capacitance

Added Note 33

Added Note 34

Removed Notes 15 and 17

Updated Pin Definitions for CQ0, CQ0_,CQ1_,and CQ1

Removed -100 Speed bin from Table.1 Selection Guide

Changed voltage name from V_DDQto V_DDIO

Changed voltage name from V_DDto V_CORE

Moved the Mailbox Interrupt Timing Diagram to be the final timing diagram

Updated the Package Type for the CYD36S18V18 parts

Updated the Package Type for the CYD18S18V18 parts

Updated the Package Type for the CYD18S36V18 parts

Included the Package Diagram for the 256-Ball FBGA (19 x 19 mm) BW256

Included an OE Controlled Write for Flow-Through Mode Switching Waveform

Included a Read with Echo Clock Switching Waveform

Updated Figure 5 and Figure 6

Updated Electrical Characteristics for READY V_OHand READY V

Updated Electrical Characteristics for V_OHand V_OLfor the -167 and -133 speeds

Included a Unit column for Table 5

Removed Switching Characteristic t_CAfrom chart

Included t_OHZin Switching Waveform OE Controlled Write for Pipelined Mode

Included t_CKLZ2in Waveform Read-to-Write-to-Read for Flow-Through Mode

402238 SEE ECN

KGH

Updated AC Test Load and Waveforms

Included FullFlex36 SDR 484-ball BGA Pinout (Top View)

Included FullFlex18 SDR 484-ball BGA Pinout (Top View)

Included Timing Parameter t_CORDY

Document #: 38-06082 Rev. *C

Page 48 of 48

1...45 46 4748

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与CYD36S72V18-133BBI相关器件

型号	品牌	描述	获取价格	数据表
CYD36S72V18-133BGI	CYPRESS	Dual-Port SRAM, 512KX72, 13ns, CMOS, PBGA484, 27 X 27 MM, 2.33 MM HEIGHT, 1 MM PITCH, PLAS	获取价格
CYD36S72V18-133BGXC	CYPRESS	Dual-Port SRAM, 512KX72, 13ns, CMOS, PBGA484, 27 X 27 MM, 2.33 MM HEIGHT, 1 MM PITCH, LEAD	获取价格
CYD36S72V18-133BGXI	CYPRESS	Dual-Port SRAM, 512KX72, 13ns, CMOS, PBGA484, 27 X 27 MM, 2.33 MM HEIGHT, 1 MM PITCH, LEAD	获取价格
CYD36S72V18-167BGXC	CYPRESS	Dual-Port SRAM, 512KX72, 11ns, CMOS, PBGA484, 27 X 27 MM, 2.33 MM HEIGHT, 1 MM PITCH, LEAD	获取价格
CYD36S72V18-167BGXI	CYPRESS	FullFlex Synchronous SDR Dual Port SRAM Commercial and Industrial temperature	获取价格
CYD36S72V18-167BGXI	ROCHESTER	512KX72 DUAL-PORT SRAM, 4ns, PBGA484, 27 X 27 MM, 2.33 MM HEIGHT, 1 MM PITCH, LEAD FREE, P	获取价格

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