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CY8CPLC10-28PVXIT PDF预览

CY8CPLC10-28PVXIT

更新时间: 2024-11-20 06:51:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 通信
页数 文件大小 规格书
25页 1336K
描述
Powerline Communication Solution

CY8CPLC10-28PVXIT 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:SSOP包装说明:SSOP, SSOP28,.3
针数:28Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.31.00.01
风险等级:5.08JESD-30 代码:R-PDSO-G28
JESD-609代码:e3长度:10.2 mm
湿度敏感等级:3端子数量:28
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP28,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
座面最大高度:2 mm子类别:Other uPs/uCs/Peripheral ICs
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:5.3 mm
uPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUITBase Number Matches:1

CY8CPLC10-28PVXIT 数据手册

 浏览型号CY8CPLC10-28PVXIT的Datasheet PDF文件第2页浏览型号CY8CPLC10-28PVXIT的Datasheet PDF文件第3页浏览型号CY8CPLC10-28PVXIT的Datasheet PDF文件第4页浏览型号CY8CPLC10-28PVXIT的Datasheet PDF文件第5页浏览型号CY8CPLC10-28PVXIT的Datasheet PDF文件第6页浏览型号CY8CPLC10-28PVXIT的Datasheet PDF文件第7页 
CY8CPLC10  
Powerline Communication Solution  
Features  
Functional Overview  
Integrated Powerline Modem PHY  
The CY8CPLC10 is an integrated Powerline Communication  
solution with the Powerline Modem PHY and Powerline Network  
Protocol Stack on the same chip. This helps in robust communi-  
cation between different nodes on a Powerline.  
2400 bps Frequency Shift Keying Modulation  
Powerline Optimized Network Protocol  
Integrates Data Link, Transport, and Network Layers  
Supports Bidirectional Half-Duplex Communication  
CRC Error Detection to Minimize Data Loss  
I2C enabled Powerline Application Layer  
Supports I2C Frequencies of 50, 100, and 400 kHz  
Powerline Transmitter  
The application residing on a host microcontroller generates  
messages to be transmitted on the Powerline. These messages  
are delivered to the CY8CPLC10 over an I2C serial link.  
The Powerline Network Layer residing on the CY8CPLC10  
receives these I2C messages and generates a Powerline Trans-  
ceiver (PLT) packet. These packets are modulated by the FSK  
Modem and coupled with Powerline by the external coupling  
circuit.  
Reference Designs for 110V to 240V AC, 12V to 24V AC/DC  
Coupling Circuits  
Reference Designs Comply with CENELEC EN50065-1:2001  
and FCC Part 15  
Powerline Receiver  
Powerline signals are received by the coupling circuit and  
demodulated by the FSK Modem PHY. These PLT packets are  
decoded by the Powerline Network Protocol and then transferred  
to the external host microcontroller in an I2C format.  
Applications  
Residential and commercial lighting control  
Home automation  
Automatic meter reading  
Industrial control and signage  
Smart energy management  
Logic Block Diagram  
Host System  
Powerline Communication Solution  
PSoCTM  
External µC  
/
Powerline Network  
I2C Packet  
Protocol  
Powerline  
FSK Modem  
PHY  
Application  
Circuitry  
AC/DC Powerline  
Coupling Circuit  
(110V-240V AC, 12V-24V  
AC/DC, etc.)  
Powerline  
Cypress Semiconductor Corporation  
Document Number: 001-50001 Rev *C  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised August 21, 2009  
[+] Feedback  

CY8CPLC10-28PVXIT 替代型号

型号 品牌 替代类型 描述 数据表
CY8CPLC10-28PVXI CYPRESS

完全替代

Powerline Communication Solution

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