Datasheet > CY8CPLC20_11

CY8CPLC20_11

更新时间： 2024-11-20 12:20:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		通信
页数	文件大小	规格书
56页	867K
描述
Powerline Communication Solution Frequency shift keying modulation

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY8CPLC20_11 数据手册

CY8CPLC20

Powerline Communication Solution

Features

■ Powerline communication solution

■ Flexible on-chip memory

❐ Integrated powerline modem PHY

❐ Frequency shift keying modulation

❐ 32 KB flash program storage 50,000 erase or write cycles

❐ 2 KB SRAM data storage

❐ Configurable baud rates up to 2400 bps

❐ Powerline optimized network protocol

❐ EEPROM emulation in flash

■ Programmable pin configurations

❐ 25 mA sink, 10 mA source on all GPIOs

❐ Pull-up, Pull-down, high Z, strong, or open drain drive

Modes on all GPIO

❐ Integrates data link, transport, and network layers

❐ Supports bidirectional half duplex communication

❐ 8-bit CRC error detection to minimize data loss

❐ I²C enabled powerline application layer

❐ Supports I²C frequencies of 50, 100, and 400 kHz

❐ Up to 12 analog inputs on all GPIOs

❐ Configurable interrupt on all GPIOs

❐ Reference designs for 110 V/240 V AC and 12 V/24 V

■ Additional system resources

AC/DC Powerlines

❐ I²C slave, master, and multi-master to 400 kHz

❐ Watchdog and sleep timers

❐ Reference designs comply with CENELEC EN

50065-1:2001 and FCC Part 15

❐ User-configurable low-voltage detection

❐ Integrated supervisory circuit

❐ On-chip precision voltage reference

■ Powerful Harvard-architecture Processor

❐ M8C processor speeds to 24 MHz

❐ Two 8x8 multiply, 32-bit accumulate

■ Programmable system resources (PSoC^®Blocks)

❐ 12 Rail-to-Rail Analog PSoC Blocks provide:

• Up to 14-bit ADCs

• Up to 9-bit DACs

• Programmable gain amplifiers

• Programmable filters and comparators

❐ 16 Digital PSoC Blocks provide:

• 8 to 32-bit Timers, Counters, and PWMs

• CRC and PRS Modules

■ Complete development tools

❐ Free development software (PSoC Designer™)

❐ Full-featured in-circuit emulator (ICE) and programmer

❐ Full-speed emulation

❐ Complex breakpoint structure

❐ 128 KB trace memory

❐ Complex events

❐ C Compilers, assembler, and linker

• Up to four full duplex UARTs

• Multiple SPI™ masters or slaves

• Connectable to all GPIO Pins

❐ Complex peripherals by combining blocks

Logic Block Diagram

Powerline Communication Solution

Embedded Application

Powerline Network

Protocol

Programmable

System Resources

Digital and Analog

Peripherals

Additional System

Physical Layer FSK

Modem

Resources

MAC, Decimator, I2C,

SPI, UART etc.

PLC Core

PSoC Core

Powerline Transceiver Packet

AC/DC Powerline Coupling Circuit

(110V/240V AC, 12V/24V AC/DC etc.)

Powerline

Cypress Semiconductor Corporation

Document Number: 001-48325 Rev. *J

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 29, 2011

12 3 4 5 6 7...56

中文翻译

下载PDF

与CY8CPLC20_11相关器件

型号	品牌	获取价格	描述	数据表
CY8CPLC20_12	CYPRESS	获取价格	Powerline Communication Solution
CY8CPLC20-28PVXI	CYPRESS	获取价格	Powerline Communication Solution
CY8CPLC20-28PVXIT	CYPRESS	获取价格	Powerline Communication Solution
CY8CPLC20-48LFXI	CYPRESS	获取价格	Powerline Communication Solution
CY8CPLC20-48LTXI	CYPRESS	获取价格	Powerline Communication Solution
CY8CPLC20-48LTXI	INFINEON	获取价格	Powerline Communications
CY8CPLC20-48LTXIT	CYPRESS	获取价格	Powerline Communication Solution
CY8CPLC20-48LTXIT	INFINEON	获取价格	Powerline Communications
CY8CPLC20-OCD	CYPRESS	获取价格	Powerline Communication Solution
CY8CTMA1036	CYPRESS	获取价格	Automotive TrueTouchÂ® Multi-Touch All-Points

与CY8CPLC20_11相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

25
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

17
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

49
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

46

产品中心

服务支持

精选活动

关于我们

帮助中心

CY8CPLC20_11

CY8CPLC20_11 数据手册

与CY8CPLC20_11相关器件

与CY8CPLC20_11相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY8CPLC20_11

CY8CPLC20_11 数据手册

与CY8CPLC20_11相关器件

与CY8CPLC20_11相关文章

您还可以找

您在本页遇到什么问题？