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CY8CLED04D01 PDF预览

CY8CLED04D01

更新时间: 2022-12-21 13:34:38
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 驱动器
页数 文件大小 规格书
52页 1388K
描述
PowerPSoC Intelligent LED Driver

CY8CLED04D01 数据手册

 浏览型号CY8CLED04D01的Datasheet PDF文件第43页浏览型号CY8CLED04D01的Datasheet PDF文件第44页浏览型号CY8CLED04D01的Datasheet PDF文件第45页浏览型号CY8CLED04D01的Datasheet PDF文件第47页浏览型号CY8CLED04D01的Datasheet PDF文件第48页浏览型号CY8CLED04D01的Datasheet PDF文件第49页 
CY8CLED04D01, CY8CLED04D02  
CY8CLED04G01, CY8CLED03D01  
CY8CLED03D02, CY8CLED03G01  
CY8CLED02D01, CY8CLED01D01  
15.18 PSoC Core Programming Specifications  
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and T 115°C. Typical parameters apply to 5V at 25°C. These are for design guidance only.  
J
Table 15-32. Programming DC Specifications  
Symbol  
IDDP  
Description  
Min  
Typ  
15  
Max  
30  
Units  
mA  
V
Notes  
Supply Current During Programming or Verify  
VILP  
VIHP  
IILP  
Input Low Voltage During Programming or  
Verify  
0.8  
Input High Voltage During Programming or  
Verify  
2.1  
V
mA  
mA  
V
Input Current when Applying Vilp to P1[0] or  
P1[1] During Programming or Verify  
0.2  
1.5  
Driving internal pull down  
resistor.  
IIHP  
Input Current when Applying Vihp to P1[0] or  
P1[1] During Programming or Verify  
Driving internal pull down  
resistor.  
VOLV  
VOHV  
Output Low Voltage During Programming or  
Verify  
VSS + 0.75  
VDD  
Output High Voltage During Programming or VDD - 1.0  
Verify  
V
FlashENPB Flash Endurance (per block)  
50,000  
Erase/write cycles per  
block.  
FlashENT Flash Endurance (total)[7]  
1,800,000  
10  
Erase/write cycles.  
FlashDR  
Flash Data Retention[8]  
Years  
Table 15-33. Programming AC Specifications  
Symbol  
tRSCLK  
tFSCLK  
tSSCLK  
tHSCLK  
fSCLK  
Description  
Rise Time of SCLK  
Min  
1
Typ  
Max  
20  
20  
Units  
ns  
Notes  
Fall Time of SCLK  
1
ns  
Data Set up Time to Falling Edge of SCLK  
Data Hold Time from Falling Edge of SCLK  
Frequency of SCLK  
40  
40  
0
ns  
ns  
8
MHz  
ms  
ms  
ns  
tERASEB  
tWRITE  
tDSCLK  
Flash Erase Time (Block)  
10  
30  
Flash Block Write Time  
Data Out Delay from Falling Edge of SCLK  
50  
Notes  
7. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks  
of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees  
more than 50,000 cycles)  
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.  
Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.  
8. Guaranteed for -40°C T 85°C  
A
Document Number: 001-46319 Rev. *G  
Page 46 of 52  
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