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CY8C5588LTI-114 PDF预览

CY8C5588LTI-114

更新时间: 2024-01-15 08:33:36
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟
页数 文件大小 规格书
102页 2766K
描述
Multifunction Peripheral, CMOS, 8 X 8 MM, 0.40 MM HEIGHT, ROHS COMPLAINT, MO-220, QFN-68

CY8C5588LTI-114 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFN
包装说明:8 X 8 MM, 0.40 MM HEIGHT, ROHS COMPLAINT, MO-220, QFN-68针数:68
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.84地址总线宽度:
边界扫描:YES总线兼容性:USB
最大时钟频率:80 MHz外部数据总线宽度:
JESD-30 代码:S-XQCC-N68JESD-609代码:e4
长度:8 mm湿度敏感等级:3
I/O 线路数量:48端子数量:68
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC68,.32SQ,16封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:1.8/5 V认证状态:Not Qualified
RAM(字数):32768ROM大小(位):262144 Bits
座面最大高度:1 mm子类别:Other Microprocessor ICs
最大供电电压:5.5 V最小供电电压:1.71 V
标称供电电压:1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:NO LEAD
端子节距:0.4 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20紫外线可擦:N
宽度:8 mmBase Number Matches:1

CY8C5588LTI-114 数据手册

 浏览型号CY8C5588LTI-114的Datasheet PDF文件第96页浏览型号CY8C5588LTI-114的Datasheet PDF文件第97页浏览型号CY8C5588LTI-114的Datasheet PDF文件第98页浏览型号CY8C5588LTI-114的Datasheet PDF文件第99页浏览型号CY8C5588LTI-114的Datasheet PDF文件第101页浏览型号CY8C5588LTI-114的Datasheet PDF文件第102页 
PRELIMINARY  
PSoC® 5: CY8C55 Family Datasheet  
Description Title: PSoC® 5: CY8C55 Family Datasheet Programmable System-on-Chip (PSoC®)  
Document Number: 001-44094  
*F  
2911720  
04/13/10  
MKEA  
Updated Vb pin in PCB Schematic.  
Updated Tstartup parameter in AC Specifications table.  
Added Load regulation and Line regulation parameters to Inductive Boost  
Regulator DC Specifications table.  
Updated I parameter in LCD Direct Drive DC Specs table.  
CC  
In page 1, updated internal oscillator range under Precision programmable  
clocking to start from 3 MHz.  
Updated I  
parameter in LCD Direct Drive DC Specs table.  
OUT  
Updated Table 6-2 and Table 6-3.  
Added bullets on CapSense in page 1; added CapSense column in Section  
12.  
Removed some references to footnote [1].  
Added footnote in PLL AC Specification table.  
Added PLL intermediate frequency row with footnote in PLL AC Specs table.  
Added UDBs subsection under 11.6 Digital Peripherals.  
Updated Figure 2-6 (PCB Layout). Updated Pin Descriptions section and  
modified Figures 6-6, 6-8, 6-9.  
Updated LVD in Tables 6-2 and 6-3; modified Low power modes bullet in  
page 1.  
Added note to Figures 2-5 and 6-2; Updated Figure 6-2 to add capacitors for  
V
and V  
pins.  
DDA  
DDD  
Updated boost converter section (6.2.2).  
Updated Tstartup values in Table 11-3.  
Removed IPOR rows from Table 11-68.  
Updated 6.3.1.1, Power Voltage Level Monitors.  
Updated section 5.2 and Table 11-2 to correct suggestion of execution from  
flash.  
Updated V  
specs in Table 11-21.  
REF  
Updated IDAC uncompensated gain error in Table 11-25.  
Added sentence to last paragraph of section 6.1.1.3.  
Updated T  
, high and low power modes, in Table 11-24.  
RESP  
Updated f_TCK values in Table 11-73 and f_SWDCK values in Table 11-74.  
Updated SNR condition in Table 11-20.  
Corrected unit of measurement in Table 11-21.  
Updated sleep wakeup time in Table 6-3 and Tsleep in Table 11-3.  
Added 1.71 V <= V  
< 3.3 V, SWD over USBIO pins value to Table 11-74.  
DDD  
Removed mention of hibernate reset (HRES) from page 1 features, Table  
6-3, Section 6.2.1.4, Section 6.3, and Section 6.3.1.1.  
Changed PPOR/PRES to TBDs in Section 6.3.1.1, Section 6.4.1.6 (changed  
PPOR to reset), Table 11-3 (changed PPOR to PRES), Table 11-68 (changed  
title, values TBD), and Table 11-69 (changed PPOR_TR to PRES_TR).  
Added sentence saying that LVD circuits can generate a reset to Section  
6.3.1.1.  
Changed I values on page 1, page 5, and Table 11-2.  
DD  
Changed resume time value in Section 6.2.1.3.  
Changed ESD HBM value in Table 11-1.  
Changed SNR in 16-bit resolution mode value and sample rate row in Table  
11-20.  
Removed V  
= 1.65 V rows and changed BWag value in Table 11-22.  
values and changed CMRR value in Table 11-23.  
DDA  
Changed V  
IOFF  
Changed INL max value in Table 11-27.  
Added max value to the Quiescent current specs in Tables 11-29 and 11-31.  
Changed occurrences of “Block” to “Row” and deleted the “ECC not included”  
footnote in Table 11-57.  
Changed max response time value in Tables 11-69 and 11-71.  
Changed the Startup time in Table 11-79.  
Added condition to intermediate frequency row in Table 11-85.  
Added row to Table 11-69.  
Added brown out note to Section 11.8.1.  
Document Number: 001-44094 Rev. *J  
Page 100 of 102  
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