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CY8C5246AXI-054T

更新时间： 2024-01-13 20:17:21

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
85页	2770K
描述
Micro Peripheral IC, CMOS, PQFP100

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CY8C5246AXI-054T 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	QFP, QFP100,.63SQ,20	Reach Compliance Code：	unknown
风险等级：	5.81	JESD-30 代码：	S-PQFP-G100
端子数量：	100	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP100,.63SQ,20
封装形状：	SQUARE	封装形式：	FLATPACK
电源：	3/5 V	认证状态：	Not Qualified
ROM大小（位）：	524288 Bits	子类别：	Other Microprocessor ICs
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
紫外线可擦：	N	Base Number Matches：	1

CY8C5246AXI-054T 数据手册

PRELIMINARY

PSoC^®5:CY8C52FamilyData Sheet

clocks, together with programmable clock dividers, provide the

flexibility to integrate most timing requirements.

The details of the PSoC power modes are covered in the “Power

System” section on page 22 of this data sheet.

PSoC uses JTAG (4 wire) or Serial Wire Debug (SWD) (2 wire)

interfaces for programming, debug, and test. Using these

standard interfaces enables the designer to debug or program

the PSoC with a variety of hardware solutions from Cypress or

third party vendors. The Cortex-M3 debug and trace modules

include Flash Patch and Breakpoint (FPB), Data Watchpoint and

Trace (DWT), Embedded Trace Macrocell (ETM), and Instru-

mentation Trace Macrocell (ITM). These modules have many

features to help solve difficult debug and trace problems. Details

of the programming, test, and debugging interfaces are

discussed in the “Programming, Debug Interfaces, Resources”

section on page 51 of this data sheet.

The CY8C52 family supports a wide supply operating range from

1.71 to 5.5V. This allows operation from regulated supplies such

as 1.8 ± 5%, 2.5V ±10%, 3.3V ± 10%, or 5.0V ± 10%, or directly

from a wide range of battery types. In addition, it provides an

integrated high efficiency synchronous boost converter that can

power the device from supply voltages as low as 0.5V. This

enables the device to be powered directly from a single battery

or solar cell. In addition, the designer can use the boost converter

to generate other voltages required by the device, such as a 3.3V

supply for LCD glass drive. The boost’s output is available on the

Vboost pin, allowing other devices in the application to be

powered from the PSoC.

2. Pinouts

PSoC supports a wide range of low power modes. These include

a 300 nA hibernate mode with RAM retention and a 2 µA sleep

mode with real time clock (RTC). In the second mode the

optional 32.768 kHz watch crystal runs continuously and

maintains an accurate RTC.

The Vddio pin that supplies a particular set of pins is indicated

by the black lines drawn on the pinout diagrams in Figure 2-1

through Figure 2-3. Using the Vddio pins, a single PSoC can

support multiple interface voltage levels, eliminating the need for

off-chip level shifters. Each Vddio may sink up to 100 mA total to

its associated I/O pins. On the 68 pin and 100 pin devices each

set of Vddio associated pins may sink up to 100 mA. The 48 pin

device may sink up to 100 mA total for all Vddio0 plus Vddio2

associated I/O pins and 100 mA total for all Vddio1 plus Vddio3

associated I/O pins.

Power to all major functional blocks, including the programmable

digital and analog peripherals, can be controlled independently

by firmware. This allows low power background processing

when some peripherals are not in use. This, in turn, provides a

total device current of only 2 mA when the CPU is running at

6 MHz.

[2]

Figure 2-1. 48-Pin SSOP Part Pinout

(SIO) P12[2]

(SIO) P12[3]

Vdda

Vssa

Lines show

Vddio to I/O

supply

(GPIO) P0[0]

(GPIO) P0[1]

(GPIO) P0[2]

(Extref0, GPIO) P0[3]

Vddio0

46 Vcca

45 P15[3] (GPIO, kHz XTAL: Xi)

44 P15[2] (GPIO, kHz XTAL: Xo)

association

P12[1] (SIO, I2C1: SDA)

42 P12[0] (SIO, I2C1: SCL)

41 Vddio3

(GPIO) P0[4]

(GPIO) P0[5]

40 P15[1] (GPIO, MHz XTAL: Xi)

39 P15[0] (GPIO, MHz XTAL: Xo)

(GPIO) P0[6] 10

(GPIO) P0[7]

Vccd 12

Vssd

Vddd 14

Vccd

37 Vssd

Vddd

35 P15[7] (USBIO, D-, SWDCK)

SSOP

[2]

(TRACECLK, GPIO) P2[3]

P15[6] (USBIO, D+, SWDIO)

P1[7] (GPIO)

(TRACEDATA[0], GPIO) P2[4]

Vddio2

P1[6] (GPIO)

(TRACEDATA[1], GPIO) P2[5]

Vddio1

(TRACEDATA[2], GPIO) P2[6] 19

30 P1[5] (GPIO, nTRST)

(TRACEDATA[3], GPIO) P2[7]

P1[4] (GPIO, TDI)

Vssb

Ind

P1[3] (GPIO, TDO, SWV)

P1[2] (GPIO, configurable XRES)

Vboost 23

Vbat 24

26 P1[1] (GPIO, TCK, SWDCK)

25 P1[0] (GPIO, TMS, SWDIO)

Document Number: 001-55034 Rev. *A

Page 5 of 85

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与CY8C5246AXI-054T相关器件

型号	品牌	获取价格	描述	数据表
CY8C5246AXI-093	CYPRESS	获取价格	Programmable System-on-Chip (PSoC)
CY8C5246LTI-029	CYPRESS	获取价格	Programmable System-on-Chip (PSoC)
CY8C5246LTI-087	CYPRESS	获取价格	Programmable System-on-Chip (PSoC)
CY8C5246PVI-012	CYPRESS	获取价格	Programmable System-on-Chip (PSoC)
CY8C5246PVI-071	CYPRESS	获取价格	Programmable System-on-Chip (PSoC)
CY8C5246PVI-091	CYPRESS	获取价格	Programmable System-on-Chip (PSoC)
CY8C5246PVI-092	CYPRESS	获取价格	Programmable System-on-Chip (PSoC)
CY8C5247AXI-013	CYPRESS	获取价格	Programmable System-on-Chip (PSoC)
CY8C5247AXI-051	CYPRESS	获取价格	Programmable System-on-Chip (PSoC)
CY8C5247AXI-086	CYPRESS	获取价格	Programmable System-on-Chip (PSoC)

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