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CY8C5247PVI-074

更新时间： 2024-11-05 06:51:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 多功能外围设备微控制器和处理器光电二极管时钟
页数 文件大小 规格书
85页 2770K
描述
Programmable System-on-Chip (PSoC)

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CY8C5247PVI-074 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP, SSOP48,.4针数：48
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.84Is Samacsys：N
地址总线宽度：边界扫描：YES
最大时钟频率：40 MHz外部数据总线宽度：
JESD-30 代码：R-PDSO-G48JESD-609代码：e3
长度：15.875 mm湿度敏感等级：3
I/O 线路数量：31端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP48,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：2/5 V认证状态：Not Qualified
RAM（字数）：64000ROM大小（位）：1048576 Bits
座面最大高度：2.79 mm子类别：Other Microprocessor ICs
最大供电电压：5.5 V最小供电电压：1.71 V
标称供电电压：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：20紫外线可擦：N
宽度：7.505 mmBase Number Matches：1

CY8C5247PVI-074 数据手册

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PRELIMINARY  
PSoC®5: CY8C52 Family Data Sheet  
Programmable System-on-Chip (PSoC®)  
General Description  
With its unique array of configurable blocks, PSoC®5 is a true system level solution providing MCU, memory, analog, and digital  
peripheral functions in a single chip. The CY8C52 family offers a modern method of signal acquisition, signal processing, and control  
with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to  
ultrasonic signals. The CY8C52 family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The  
CY8C52 family is also a high performance configurable digital system with some part numbers including interfaces such as USB,  
multi-master I2C, and CAN. In addition to communication interfaces, the CY8C52 family has an easy to configure logic array, flexible  
routing to all I/O pins, and a high performance 32-bit ARM® Cortex™-M3 microprocessor core. Designers can easily create system  
level designs using a rich library of prebuilt components and boolean primitives using PSoC® Creator™, a hierarchical schematic  
design entry tool. The CY8C52 family provides unparalleled opportunities for analog and digital bill of materials integration while easily  
accommodating last minute design changes through simple firmware updates.  
• SPI, UART, I2C  
• Many others available in catalog  
Library of advanced peripherals  
• Cyclic Redundancy Check (CRC)  
• Pseudo Random Sequence (PRS) generator  
• LIN Bus 2.0  
Features  
„
32-bit ARM Cortex-M3 CPU core  
‡
‡
DC to 40 MHz operation  
‡
Flash program memory, up to 256 KB, 100,000 write cycles,  
20 year retention, multiple security features  
‡
‡
‡
Up to 64 KB SRAM memory  
• Quadrature decoder  
Analog peripherals (1.71V ≤ Vdda ≤ 5.5V)  
2 KB EEPROM memory, 1 million cycles, 20 years retention  
24 channel DMA with multilayer AHB bus access  
• Programmable chained descriptors and priorities  
• High bandwidth 32-bit transfer support  
„
„
‡
1.024V±0.1% internal voltage reference across -40°C to  
+85°C (14 ppm/°C)  
‡
‡
SAR ADC, 12-bit at 1 Msps[1]  
Two comparators with 75 ns response time  
„
Low voltage, ultra low power  
‡
Wide operating voltage range: 0.5V to 5.5V  
Programming, debug, and trace  
JTAG(4wire), SerialWireDebug(SWD)(2wire), SingleWire  
Viewer (SWV), and TRACEPORT interfaces  
Cortex-M3 Flash Patch and Breakpoint (FPB) block  
Cortex-M3 Embedded Trace Macrocell™ (ETM™) gener-  
ates an instruction trace stream.  
Cortex-M3 Data Watchpoint and Trace (DWT) generates  
data trace information  
Cortex-M3 Instrumentation Trace Macrocell (ITM) can be  
used for printf-style debugging  
‡
Highefficiencyboostregulatorfrom0.5Vinputto1.8Vto5.0V  
output  
‡
‡
‡
2 mA at 6 MHz  
Low power modes including:  
‡
‡
• 300 nA hibernate mode with RAM retention and LVD  
• 2 µA sleep mode with real time clock and low voltage reset  
‡
‡
‡
‡
„
Versatile I/O system  
‡
‡
‡
‡
‡
‡
‡
28 to 72 I/O (62 GPIO, 8 SIO, 2 USBIO[1]  
)
Any GPIO to any digital or analog peripheral routability  
LCD direct drive from any GPIO, up to 46x16 segments[1]  
1.2V to 5.5V I/O interface voltages, up to 4 domains  
Maskable, independent IRQ on any pin or port  
Schmitt trigger TTL inputs  
DWT, ETM, andITMblockscommunicatewithoff-chipdebug  
and trace systems via the SWV or TRACEPORT  
Bootloader programming supportable through I2C, SPI,  
UART, USB, and other interfaces  
„
„
Precision, programmable clocking  
1 to 72 MHz internal ±1% oscillator (over full temperature and  
voltage range) with PLL  
4 to 33 MHz crystal oscillator for crystal PPM accuracy  
Internal PLL clock generation up to 40 MHz  
32.768 kHz watch crystal oscillator  
All GPIO configurable as open drain high/low, pull up/down,  
High-Z, or strong output  
‡
‡
‡
Configurable GPIO pin state at power on reset (POR)  
25 mA sink on SIO  
‡
‡
‡
‡
„
Digital peripherals  
‡
‡
‡
‡
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20 to 24 programmable PLD based Universal Digital Blocks  
Full CAN 2.0b 16 RX, 8 TX buffers[1]  
Low power internal oscillator at 1 kHz, 100 kHz  
Temperature and packaging  
-40°C to +85°C degrees industrial temperature  
48-pin SSOP, 68-pin QFN, and 100-pin TQFP package  
options  
Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator[1]  
Four 16-bit configurable timer, counter, and PWM blocks  
Library of standard peripherals  
‡
‡
• 8, 16, 24, and 32-bit timers, counters, and PWMs  
Note  
1. This feature on select devices only. See Ordering Information on page 79 for details.  
Cypress Semiconductor Corporation  
•
198 Champion Court  
•
San Jose  
,
CA 95134-1709  
•
408-943-2600  
Document Number: 001-55034 Rev. *A  
Revised December 03, 2009  
[+] Feedback  
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