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CY8C4244AZI-443 PDF预览

CY8C4244AZI-443

更新时间: 2024-11-07 00:47:23
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赛普拉斯 - CYPRESS /
页数 文件大小 规格书
45页 1008K
描述
Programmable System-on-Chip (PSoC®)

CY8C4244AZI-443 数据手册

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PSoC® 4: PSoC 4200  
Family Datasheet  
Programmable System-on-Chip (PSoC®)  
General Description  
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of mixed-signal programmable embedded system  
controllers with an ARM® Cortex™-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible  
automatic routing. The PSoC 4200 product family, based on this platform, is a combination of a microcontroller with digital program-  
mable logic, high-performance analog-to-digital conversion, opamps with Comparator mode, and standard communication and timing  
peripherals. The PSoC 4200 products will be fully upward compatible with members of the PSoC 4 platform for new applications and  
design needs. The programmable analog and digital sub-systems allow flexibility and in-field tuning of the design.  
Features  
32-bit MCU Sub-system  
Serial Communication  
48-MHz ARM Cortex-M0 CPU with single cycle multiply  
Up to 32 kB of flash with Read Accelerator  
Up to 4 kB of SRAM  
Two independent run-time reconfigurable serial communi-  
cation blocks (SCBs) with reconfigurable I2C, SPI, or UART  
functionality  
Timing and Pulse-Width Modulation  
Programmable Analog  
Four 16-bit timer/counter pulse-width modulator (TCPWM)  
blocks  
Two opamps with reconfigurable high-drive external and  
high-bandwidth internal drive, Comparator modes, and ADC  
input buffering capability  
Center-aligned, Edge, and Pseudo-random modes  
12-bit, 1-Msps SAR ADC with differential and single-ended  
modes; Channel Sequencer with signal averaging  
Comparator-based triggering of Kill signals for motor drive and  
other high-reliability digital logic applications  
Two current DACs (IDACs) for general-purpose or capacitive  
sensing applications on any pin  
Up to 36 Programmable GPIOs  
Two low-power comparators that operate in Deep Sleep mode  
Any GPIO pin can be CapSense, LCD, analog, or digital  
Drive modes, strengths, and slew rates are programmable  
Programmable Digital  
Four programmable logic blocks called universal digital blocks,  
(UDBs), each with 8 Macrocells and data path  
Five different packages  
48-pin TQFP, 44-pin TQFP, 40-pin QFN, 35-ball WLCSP, and  
28-pin SSOP package  
Cypress-provided peripheral component library, user-defined  
state machines, and Verilog input  
35-ball WLCSP package is shipped with I2C Bootloader in  
Flash  
Low Power 1.71-V to 5.5-V Operation  
20-nA Stop Mode with GPIO pin wakeup  
Extended Industrial Temperature Operation  
Hibernate and Deep Sleep modes allow wakeup-time versus  
power trade-offs  
–40 °C to + 105 °C operation  
PSoC Creator Design Environment  
Capacitive Sensing  
Integrated Development Environment (IDE) provides  
schematic design entry and build (with analog and digital  
automatic routing)  
Cypress CapSense Sigma-Delta (CSD) provides best-in-class  
SNR (>5:1) and water tolerance  
Cypress-supplied software component makes capacitive  
sensing design easy  
Applications Programming Interface (API) component for all  
fixed-function and programmable peripherals  
Automatic hardware tuning (SmartSense™)  
Industry-Standard Tool Compatibility  
Segment LCD Drive  
After schematic entry, development can be done with  
ARM-based industry-standard development tools  
LCD drive supported on all pins (common or segment)  
Operates in Deep Sleep mode with 4 bits per pin memory  
Cypress Semiconductor Corporation  
Document Number: 001-87197 Rev. *J  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised July 10, 2017  

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