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CY8C41223-24SXIT PDF预览

CY8C41223-24SXIT

更新时间: 2024-11-30 04:38:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 多功能外围设备微控制器和处理器光电二极管时钟
页数 文件大小 规格书
36页 827K
描述
Linear Power PSoC⑩ Devices

CY8C41223-24SXIT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP,
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.84
Is Samacsys:N边界扫描:NO
总线兼容性:I2C最大时钟频率:25 MHz
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:9.893 mm湿度敏感等级:3
I/O 线路数量:10端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260认证状态:Not Qualified
RAM(字数):256座面最大高度:1.727 mm
最大供电电压:36 V最小供电电压:2.5 V
标称供电电压:2.7 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN (800)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:3.8985 mm
Base Number Matches:1

CY8C41223-24SXIT 数据手册

 浏览型号CY8C41223-24SXIT的Datasheet PDF文件第2页浏览型号CY8C41223-24SXIT的Datasheet PDF文件第3页浏览型号CY8C41223-24SXIT的Datasheet PDF文件第4页浏览型号CY8C41223-24SXIT的Datasheet PDF文件第5页浏览型号CY8C41223-24SXIT的Datasheet PDF文件第6页浏览型号CY8C41223-24SXIT的Datasheet PDF文件第7页 
CY8C41123 and CY8C41223  
PRELIMINARY  
Linear Power PSoC™ Devices  
• 2 Comparators with DAC References  
• 6- to 12-Bit ADC (20 Ksps at 8 Bits)  
• Configurable Analog Mux, 10:1 or 5:2 Differential  
• Configurable Digital Blocks  
1.0 Features  
1.1  
Key Features  
• Extended Operating Voltage of 2.5V to 36V  
• 2 HV Linear Opamp Control Loops for Driving Power PFETs  
8- to 16-Bit Timers and Counters  
Connectable to All GPIO Pins  
• 2 HV Analog Sense Inputs  
• 4KB of Flash  
Digital Blocks can Drive Outputs to 36V  
Complex Peripherals by Combining Blocks  
• 256 Bytes of SRAM  
1.3  
Applications  
1.2  
Improved Features  
• Battery Chargers (Linear or Fly Back)  
• White LED Drivers  
• Very Low Current Mode for 100 nA Sleep (Deep Sleep)  
• Analog Absolute Accuracy (0.75%)  
• Additional Flexibility for Sleep Modes  
Temperature Sensor (Thermistor, Thermocouple)  
2.0 Block Diagram  
LowDrop-Out  
Regulator  
ANALOG and HIGH VOLTAGE  
SECTIONS  
HVdd  
InternalVdd  
ODAC1  
ODAC0  
VBG  
VDAC1  
VDAC0  
VDAC1  
VDAC0  
IBIAS  
GDO1  
VS1  
GDO0  
VS0  
Analogto  
Digital  
Convertor  
P0[7]  
P0[5]  
P0[3]  
P0[1]  
P1[1]  
P0[6]  
P0[4]  
P0[2]  
P0[0]  
P1[0]  
Atten1  
Atten0  
AMuxBus3  
AMuxBus1  
AMuxBus2  
AMuxBus0  
SYSTEMRESOURCES  
PSoCCORE  
LowSpeed  
Oscillator  
SleepandWatchdog  
COMP1  
COMP0  
POR andLVD  
Internal  
Voltage  
Reference  
ODAC1  
ODAC0  
M8CCPU  
Internal  
Main  
Oscillator  
4KBFlash  
GlobalDigitalInterconnectBus  
System Bus  
256BSRAM  
I2C  
DBC00  
DBC01  
DBD02  
DBD03  
SystemResets  
Digital  
Clocks  
DigitalPSoCBlockArray  
InterruptController  
DIGITAL SYSTEM  
Figure 2-1. Block Diagram  
Cypress Semiconductor Corporation  
Document 001-00360 Rev. *A  
198 Champion Court  
San Jose, CA 95134  
408.943.2600  
Revised November 17, 2005  

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