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CY8C3665PVI-007 PDF预览

CY8C3665PVI-007

更新时间: 2024-11-11 06:51:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 多功能外围设备微控制器和处理器光电二极管时钟
页数 文件大小 规格书
99页 2889K
描述
Programmable System-on-Chip (PSoC)

CY8C3665PVI-007 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:0.300 INCH, ROHS COMPLIANT, SSOP-48针数:48
Reach Compliance Code:unknownECCN代码:3A991.A.3
HTS代码:8542.31.00.01风险等级:5.6
Is Samacsys:N地址总线宽度:
位大小:8边界扫描:YES
总线兼容性:I2C; USBCPU系列:8051
最大时钟频率:67 MHz外部数据总线宽度:
JESD-30 代码:R-PDSO-G48JESD-609代码:e4
长度:15.875 mm湿度敏感等级:3
I/O 线路数量:25端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP48,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:2/5 V认证状态:Not Qualified
RAM(字节):4096RAM(字数):4000
ROM(单词):32768ROM可编程性:FLASH
座面最大高度:2.794 mm速度:67 MHz
子类别:Microcontrollers最大供电电压:5.5 V
最小供电电压:1.71 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:7.505 mmBase Number Matches:1

CY8C3665PVI-007 数据手册

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PRELIMINARY  
PSoC®3: CY8C36 Family Data Sheet  
Programmable System-on-Chip (PSoC®)  
General Description  
With its unique array of configurable blocks, PSoC®3 is a true system level solution providing MCU, memory, analog, and digital  
peripheral functions in a single chip. The CY8C36 family offers a modern method of signal acquisition, signal processing, and control  
with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to  
ultrasonic signals. The CY8C36 family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The  
CY8C36 family is also a high performance configurable digital system with some part numbers including interfaces such as USB,  
multi-master I2C, and CAN. In addition to communication interfaces, the CY8C36 family has an easy to configure logic array, flexible  
routing to all I/O pins, and a high performance single cycle 8051 microprocessor core. Designers can easily create system level  
designs using a rich library of prebuilt components and boolean primitives using PSoC® Creator™, a hierarchical schematic design  
entry tool. The CY8C36 family provides unparalleled opportunities for analog and digital bill of materials integration while easily  
accommodating last minute design changes through simple firmware updates.  
Features  
„
Single cycle 8051 CPU core  
• SPI, UART, I2C  
• Many others available in catalog  
Library of advanced peripherals  
• Cyclic Redundancy Check (CRC)  
• Pseudo Random Sequence (PRS) generator  
• LIN Bus 2.0  
• Quadrature decoder  
Analog peripherals (1.71V Vdda 5.5V)  
1.024V±0.9% internal voltage reference across -40°C to  
+85°C (14 ppm/°C)  
Configurable Delta-Sigma ADC with 12-bit resolution  
• Programmable gain stage: x0.25 to x16  
‡
‡
‡
DC to 67 MHz operation  
Multiply and divide instructions  
Flash program memory, up to 64 KB, 100,000 write cycles,  
20 years retention, multiple security features  
Up to 8 KB Flash ECC or configuration storage  
Up to 8 KB SRAM memory  
Up to 2 KB EEPROM memory, 1M cycles, 20 years retention  
24 channel DMA with multilayer AHB bus access  
• Programmable chained descriptors and priorities  
• High bandwidth 32-bit transfer support  
‡
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‡
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Low voltage, ultra low power  
• 12-bit mode, 192 ksps, 70 dB SNR, 1 bit INL/DNL  
‡
Wide operating voltage range: 0.5V to 5.5V  
‡
High efficiency boost regulator from 0.5V input to 1.8V-5.0V  
output  
‡
67 MHz, 24-bit fixed point digital filter block (DFB) to  
implement FIR and IIR filters[1]  
‡
‡
330 µA at 1 MHz, 1.2 mA at 6 MHz, 5.6 mA at 40 MHz  
Low power modes including:  
• 200 nA hibernate mode with RAM retention and LVD  
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‡
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Up to four 8-bit, 8 Msps IDACs or 1 Msps VDACs  
Four comparators with 75 ns response time  
Up to four uncommitted opamps with 25 mA drive capability  
Up to four configurable multifunction analog blocks. Example  
configurations are PGA, TIA, Mixer, and Sample and Hold  
• 1 µA sleep mode with real time clock and low voltage reset  
„
Versatile I/O system  
28 to 72 I/O (62 GPIO, 8 SIO, 2 USBIO[1]  
)
„
„
Programming, debug, and trace  
‡
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JTAG (4 wire), Serial Wire Debug (SWD) (2 wire), and Single  
Wire Viewer (SWV) interfaces  
Any GPIO to any digital or analog peripheral routability  
LCD direct drive from any GPIO, up to 46x16 segments[1]  
1.2V to 5.5V I/O interface voltages, up to 4 domains  
Maskable, independent IRQ on any pin or port  
Schmitt trigger TTL inputs  
‡
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8 address and 1 data breakpoint  
4 KB instruction trace buffer  
Bootloader programming supportable through I2C, SPI,  
UART, USB, and other interfaces  
All GPIO configurable as open drain high/low, pull up/down,  
High-Z, or strong output  
Precision, programmable clocking  
‡
‡
Configurable GPIO pin state at power on reset (POR)  
25 mA sink on SIO  
‡
1 to 66 MHz internal ±1% oscillator (over full temperature and  
voltage range) with PLL  
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4 to 33 MHz crystal oscillator for crystal PPM accuracy  
Internal PLL clock generation up to 67 MHz  
32.768 kHz watch crystal oscillator  
„
Digital peripherals  
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20 to 24 programmable PLD based Universal Digital Blocks  
Full CAN 2.0b 16 RX, 8 TX buffers[1]  
Low power internal oscillator at 1 kHz, 100 kHz  
Full-speed (FS) USB 2.0 12 Mbps using internal oscillator[1]  
Up to four 16-bit configurable timer, counter, and PWM blocks  
Library of standard peripherals  
„
Temperature and packaging  
‡
-40°C to +85°C degrees industrial temperature  
‡
48-pin SSOP, 48-pin QFN, 68-pin QFN, and 100-pin TQFP  
package options  
• 8, 16, 24, and 32-bit timers, counters, and PWMs  
Note  
1. This feature on select devices only. See Ordering Information on page 92 for details.  
Cypress Semiconductor Corporation  
198 Champion Court  
San Jose  
,
CA 95134-1709  
408-943-2600  
Document Number: 001-53413 Rev. *B  
Revised December 03, 2009  
[+] Feedback  

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