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CY8C24794-24LTXI PDF预览

CY8C24794-24LTXI

更新时间： 2024-11-25 14:56:47
品牌 Logo 应用领域
英飞凌 - INFINEON /
页数 文件大小 规格书
73页 2034K
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CY8C24x94

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CY8C24794-24LTXI 数据手册

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CY8C24094/CY8C24794  
CY8C24894/CY8C24994  
PSoC® Programmable System-on-Chip™  
PSoC® Programmable System-on-Chip  
1. Features  
■ XRES pin to support in-system serial programming (ISSP) and  
external reset control in CY8C24894  
❐ Up to 48 analog inputs on GPIOs  
❐ Two 33 mA analog outputs on GPIOs  
❐ Configurable interrupt on all GPIOs  
■ Powerful Harvard-architecture processor  
❐ M8C processor speeds up to 24 MHz  
❐ Two 8 × 8 multiply, 32-bit accumulate  
❐ Low power at high speed  
■ Precision, programmable clocking  
❐ Internal ±4% 24- / 48-MHz main oscillator  
❐ Internal oscillator for watchdog and sleep  
❐ 0.25% accuracy for USB with no external components  
❐ Operating voltage: 3 V to 5.25 V  
❐ Industrial temperature range: –40 °C to +85 °C  
❐ USB temperature range: –10 °C to +85 °C  
■ Additional system resources  
❐ I2C slave, master, and multi-master to 400 kHz  
❐ Watchdog and sleep timers  
■ Advanced peripherals (PSoC® Blocks)  
❐ Six rail-to-rail analog PSoC blocks provide:  
• Up to 14-bit analog-to-digital converters (ADCs)  
• Up to 9-bit digital-to-analog converters (DACs)  
• Programmable gain amplifiers (PGAs)  
• Programmable filters and comparators  
❐ Four digital PSoC blocks provide:  
• 8- to 32-bit timers, counters, and pulse width modulators  
(PWMs)  
❐ User-configurable low-voltage detection (LVD)  
2. Logic Block Diagram  
Analog  
Drivers  
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0  
Port 7  
• Cyclical redundancy check (CRC) and pseudo random  
sequence (PRS) modules  
• Full-duplex universal asynchronous receiver transmitter  
(UART)  
Global Digital Interconnect  
Global Analog Interconnect  
• Multiple serial peripheral interface (SPI) masters or slaves  
• Connectable to all general-purpose I/O (GPIO) pins  
❐ Complex peripherals by combining blocks  
PSoC CORE  
SRAM  
1K  
SROM Flash16 KB  
Sleep and  
Watchdog  
CPU Core (M8C)  
Interrupt  
Controller  
❐ Capacitive sensing application (CSA) capability  
■ Full speed USB (12 Mbps)  
❐ Four unidirectional endpoints  
❐ One bidirectional control endpoint  
❐ USB 2.0 compliant  
❐ Dedicated 256 byte buffer  
❐ No external crystal required  
Clock Sources  
(Includes IMO and ILO)  
DIGITAL SYSTEM  
ANALOG SYSTEM  
Analog  
Ref.  
Digital  
Block  
Array  
Analog  
Block  
Array  
■ Flexible on-chip memory  
❐ 16 KB flash program storage 50,000 erase and write cycles  
❐ 1 KB static random access memory (SRAM) data storage  
❐ ISSP  
❐ Partial flash updates  
❐ Flexible protection modes  
❐ Electrically erasable programmable read-only memory  
(EEPROM) emulation in flash  
Analog  
Input  
Muxing  
Internal  
Voltage USB  
Ref.  
Digital  
2
Decimator  
POR and LVD  
System Resets  
I2 C  
Clocks MACs Type 2  
■ Programmable pin configurations  
❐ 25-mA sink, 10-mA source on all GPIOs  
❐ Pull-up, pull-down, high Z, strong, or open-drain drive modes  
on all GPIOs  
SYSTEM RESOURCES  
Errata: For information on silicon errata, see “Errata” on page 66. Details include trigger conditions, devices affected, and proposed workaround.  
Cypress Semiconductor Corporation  
Document Number: 38-12018 Rev. AL  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised April 20, 2017  
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