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CY8C24794-SPPVX PDF预览

CY8C24794-SPPVX

更新时间: 2024-11-26 22:22:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
32页 367K
描述
PSoCTM Mixed-Signal Array

CY8C24794-SPPVX 数据手册

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PSoC™ Mixed-Signal Array  
Final Data Sheet  
CY8C24794  
Features  
Powerful Harvard Architecture Processor  
M8C Processor Speeds to 24 MHz  
Two 8x8 Multiply, 32-Bit Accumulate  
Low Power at High Speed  
Full-Speed USB (12 Mbps)  
Precision, Programmable Clocking  
Internal ±4% 24/48 MHz Oscillator  
Internal Oscillator for Watchdog and Sleep  
Four Uni-Directional Endpoints  
One Bi-Directional Control Endpoint  
USB 2.0 Compliant  
Dedicated 256 Byte Buffer  
No External Crystal Required  
.25% Accuracy for USB with no External  
Components  
3.0 to 5.25V Operating Voltage  
Industrial Temperature Range: -40°C to +85°C  
USB Temperature Range: -10°C to +85°C  
Additional System Resources  
I2CSlave, Master, and Multi-Master to  
Flexible On-Chip Memory  
Advanced Peripherals (PSoC Blocks)  
6 Rail-to-Rail Analog PSoC Blocks Provide:  
16K Flash Program Storage 50,000 Erase/  
Write Cycles  
1K SRAM Data Storage  
In-System Serial Programming (ISSP)  
Partial Flash Updates  
Flexible Protection Modes  
EEPROM Emulation in Flash  
400 kHz  
Watchdog and Sleep Timers  
User-Configurable Low Voltage Detection  
Integrated Supervisory Circuit  
On-Chip Precision Voltage Reference  
- Up to 14-Bit ADCs  
- Up to 9-Bit DACs  
- Programmable Gain Amplifiers  
- Programmable Filters and Comparators  
4 Digital PSoC Blocks Provide:  
Complete Development Tools  
Free Development Software  
Programmable Pin Configurations  
(PSoC™ Designer)  
- 8- to 32-Bit Timers, Counters, and PWMs  
- CRC and PRS Modules  
- Full-Duplex UART  
- Multiple SPIMasters or Slaves  
- Connectable to all GPIO Pins  
25 mA Sink on all GPIO  
Pull up, Pull down, High Z, Strong, or Open  
Drain Drive Modes on all GPIO  
Up to 48 Analog Inputs on GPIO  
Two 33 mA Analog Outputs on GPIO  
Configurable Interrupt on all GPIO  
Full-Featured, In-Circuit Emulator and  
Programmer  
Full Speed Emulation  
Complex Breakpoint Structure  
128K Bytes Trace Memory  
Complex Peripherals by Combining Blocks  
Capacitive Sensing Application Capability  
Analog  
Drivers  
PSoC™ Functional Overview  
Port5 Port4 Port3 Port2 Port1 Port0  
Port7  
The PSoC™ family consists of many Mixed-Signal Array with  
On-Chip Controller devices. All PSoC family devices are  
designed to replace traditional MCUs, system ICs, and the  
numerous discrete components that surround them. The PSoC  
CY8C24794 device is a unique member of the PSoC family  
because it includes a full-featured, full-speed (12 Mbps) USB  
port. Configurable analog, digital, and interconnect circuitry  
enable a high level of integration in a host of industrial, con-  
sumer, and communication applications.  
Global Digital Interconnect  
Global Analog Interconnect  
PSoC CORE  
SRAM  
1K  
SROM  
Flash 16K  
Sleep and  
Watchdog  
CPUCore(M8C)  
Interrupt  
Controller  
This architecture allows the user to create customized periph-  
eral configurations that match the requirements of each individ-  
ual application. Additionally, a fast CPU, Flash program  
memory, SRAM data memory, and configurable IO are included  
in a range of convenient pinouts and packages.  
ClockSources  
(Includes IMOandILO)  
DIGITAL SYSTEM  
ANALOG SYSTEM  
Analog  
Ref .  
The PSoC architecture, as illustrated on the left, is comprised of  
four main areas: PSoC Core, Digital System, Analog System,  
and System Resources including a full-speed USB port. Config-  
urable global busing allows all the device resources to be com-  
bined into a complete custom system. The PSoC CY8C24794  
device can have up to seven IO ports that connect to the global  
digital and analog interconnects, providing access to 4 digital  
blocks and 6 analog blocks.  
Digital  
Block  
Array  
Analog  
Block  
Array  
Internal  
Voltage USB  
Ref.  
Analog  
Input  
Muxing  
Digital  
Clocks MACs  
2
Decimator  
Type 2  
POR and LVD  
System Resets  
I2C  
SYSTEM RESOURCES  
April 14, 2005  
© Cypress Semiconductor Corp. 2004-2005 — Document No. 38-12018 Rev. *F  
1

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