CY8C23433, CY8C23533
PSoC® Programmable System-on-Chip™
Features
■ Powerful Harvard-architecture processor
❐ M8C processor speeds to 24 MHz
❐ 8x8 multiply, 32-bit accumulate
■ Complete development tools
❐ Free development software (PSoC Designer™)
❐ Full-featured in-circuit emulator and programmer
❐ Full speed emulation
❐ Low power at high speed
❐ 3.0 V to 5.25 V operating voltage
❐ Industrial temperature range: –40 °C to +85 °C
❐ Complex breakpoint structure
❐ 128 KB trace memory
■ Advanced peripherals (PSoC blocks)
❐ Four Rail-to-Rail analog PSoC blocks provide:
• Up to 14-bit ADCs
Logic Block Diagram
Analog
Port 3 Port 2 Port 1 Port 0
Drivers
• Up to 8-bit DACs
• Programmable gain amplifiers
• Programmable filters and comparators
❐ Four digital PSoC blocks provide:
• 8- to 32-bit timers and counters, 8- and 16-bit pulse-width
modulators (PWMs)
PSoC CORE
System Bus
Global Digital Interconnect
SRAM
• CRC and PRS modules
• Full-duplex UART
• Multiple SPI masters or slaves
• Connectable to all GPIO Pins
❐ Complex peripherals by combining blocks
❐ High-Speed 8-Bit SAR ADC optimized for motor control
Global Analog Interconnect
Flash 8K
SROM
256 Bytes
Sleep and
Watchdog
CPUCore(M8C)
Interrupt
Controller
MultipleClockSources
(IncludesIMO,ILO, PLL, andECO)
■ Precision, programmable clocking
❐ Internal ±2.5% 24/48 MHz oscillator
❐ High accuracy 24 MHz with optional 32 KHz crystal and PLL
❐ Optional external oscillator, up to 24 MHz
❐ Internal oscillator for watchdog and sleep
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref
Digital
Block
Array
Analog
Block Array
■ Flexible on-chip memory
2 Columns
4 Blocks
1 Row
4 Blocks
❐ 8K bytes flash program storage 50,000 erase/write cycles
❐ 256 bytes SRAM data storage
❐ In-system serial programming (ISSP)
❐ Partial flash updates
Analog
Input
Muxing
SAR8 ADC
❐ Flexible protection modes
❐ EEPROM emulation in flash
Internal
Voltage
Ref.
Digital
Clocks
Multiply
Accum.
POR and LVD
System Resets
I2C
■ Programmable pin configurations
❐ 25 mA Sink, 10 mA source on all GPIO
❐ Pull-up, pull-down, high Z, strong, or open drain drive modes
on all GPIO
Decimator
SYSTEM RESOURCES
❐ Up to eight analog inputs on GPIO plus two additional analog
inputs with restricted routing
❐ Two 30 mA analog outputs on GPIO
❐ Configurable interrupt on all GPIO
■ Additional system resources
❐ I2C slave, master, and multi-master to 400 kHz
❐ Watchdog and sleep timers
❐ User-configurable low voltage detection
❐ Integrated supervisory circuit
❐ On-chip precision voltage reference
Cypress Semiconductor Corporation
Document Number: 001-44369 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 8, 2013
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