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CY8C22213A-24LFXI PDF预览

CY8C22213A-24LFXI

更新时间： 2023-01-02 17:09:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 微控制器外围集成电路
页数 文件大小 规格书
44页 643K
描述
Microcontroller, 8-Bit, FLASH, M8C CPU, 24MHz, CMOS, PQCC32,

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CY8C22213A-24LFXI 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：QCCN, LCC32,.2SQ,20Reach Compliance Code：compliant
风险等级：5.8位大小：8
CPU系列：M8CJESD-30 代码：S-PQCC-N32
JESD-609代码：e4湿度敏感等级：3
端子数量：32最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：QCCN封装等效代码：LCC32,.2SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER
电源：2.5/5 V认证状态：Not Qualified
RAM（字节）：256ROM（单词）：2048
ROM可编程性：FLASH速度：24 MHz
子类别：Microcontrollers最大压摆率：8 mA
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUADuPs/uCs/外围集成电路类型：MULTIFUNCTION PERIPHERAL
Base Number Matches：1

CY8C22213A-24LFXI 数据手册

 浏览型号CY8C22213A-24LFXI的Datasheet PDF文件第2页浏览型号CY8C22213A-24LFXI的Datasheet PDF文件第3页浏览型号CY8C22213A-24LFXI的Datasheet PDF文件第4页浏览型号CY8C22213A-24LFXI的Datasheet PDF文件第5页浏览型号CY8C22213A-24LFXI的Datasheet PDF文件第6页浏览型号CY8C22213A-24LFXI的Datasheet PDF文件第7页 
PSoC™ Mixed Signal Array  
Preliminary Data Sheet  
CY8C22113A and CY8C22213A  
Features  
■ Powerful Harvard Architecture Processor  
■ M8C Processor Speeds to 24 MHz  
■ Low Power at High Speed  
■ Precision, Programmable Clocking  
■ Additional System Resources  
■ I2C™ Slave, Master, and Multi-Master to  
■ Internal ±2.5% 24/48 MHz Oscillator  
■ High-Accuracy 24 MHz with Optional 32.768  
kHz Crystal and PLL  
■ Optional External Oscillator, up to 24 MHz  
■ Internal Oscillator for Watchdog and Sleep  
400 kHz  
■ 2.4 to 5.25 V Operating Voltage  
■ Industrial Temperature Range: -40°C to +85°C  
■ Watchdog and Sleep Timers  
■ User-Configurable Low Voltage Detection  
■ Integrated Supervisory Circuit  
■ Advanced Peripherals (PSoC Blocks)  
■ 3 Rail-to-Rail Analog PSoC Blocks Provide:  
- Up to 14-Bit ADCs  
■ On-Chip Precision Voltage Reference  
■ Flexible On-Chip Memory  
■ 2K Bytes Flash Program Storage 50,000  
Erase/Write Cycles  
■ 256 Bytes SRAM Data Storage  
■ In-System Serial Programming (ISSP™)  
■ Partial Flash Updates  
■ Flexible Protection Modes  
■ EEPROM Emulation in Flash  
■ Complete Development Tools  
■ Free Development Software  
- Up to 9-Bit DACs  
(PSoC™ Designer)  
- Programmable Gain Amplifiers  
- Programmable Filters and Comparators  
■ 4 Digital PSoC Blocks Provide:  
- 8- to 32-Bit Timers, Counters, and PWMs  
- CRC and PRS Modules  
■ Full-Featured, In-Circuit Emulator and  
Programmer  
■ Full Speed Emulation  
■ Complex Breakpoint Structure  
■ 128K Bytes Trace Memory  
■ Programmable Pin Configurations  
- Full-Duplex UART  
- SPI™ Masters or Slaves  
- Connectable to all GPIO Pins  
■ 25 mA Sink on all GPIO  
■ Pull up, Pull down, High Z, Strong, or Open  
Drain Drive Modes on all GPIO  
■ Complex Peripherals by Combining Blocks  
■ Up to 8 Analog Inputs on GPIO  
■ One 30 mA Analog Outputs on GPIO  
■ Configurable Interrupt on all GPIO  
Analog  
PSoC™ Functional Overview  
Port 1  
Port 0  
Drivers  
PSoC CORE  
The PSoC™ family consists of many Mixed Signal Array with  
On-Chip Controller devices. These devices are designed to  
replace multiple traditional MCU-based system components  
with one, low cost single-chip programmable device. PSoC  
devices include configurable blocks of analog and digital logic,  
as well as programmable interconnects. This architecture  
allows the user to create customized peripheral configurations  
that match the requirements of each individual application.  
Additionally, a fast CPU, Flash program memory, SRAM data  
memory, and configurable IO are included in a range of conve-  
nient pinouts and packages.  
SYSTEM BUS  
Global Digital Interconnect  
Global Analog Interconnect  
SRAM  
256 Bytes  
SROM  
Flash 2K  
Sleep and  
Watchdog  
CPU Core (M8C)  
Interrupt  
Controller  
Multiple Clock Sources  
(Includes IMO, ILO, PLL, and ECO)  
The PSoC architecture, as illustrated on the left, is comprised of  
four main areas: PSoC Core, Digital System, Analog System,  
and System Resources. Configurable global busing allows all  
the device resources to be combined into a complete custom  
system. The PSoC CY8C22x13A family can have up to two IO  
ports that connect to the global digital and analog interconnects,  
providing access to 4 digital blocks and 3 analog blocks.  
DIGITAL SYSTEM  
ANALOG SYSTEM  
Analog  
Ref  
Analog  
Block  
Array  
Digital  
Block Array  
(1 Row,  
4 Blocks)  
Analog  
Input  
Muxing  
(1 Column,  
3 Blocks)  
The PSoC Core  
The PSoC Core is a powerful engine that supports a rich fea-  
ture set. The core includes a CPU, memory, clocks, and config-  
urable GPIO (General Purpose IO).  
POR and LVD  
System Resets  
Internal  
Voltage  
Ref.  
Digital  
Clocks  
Decimator  
I2C  
The M8C CPU core is a powerful processor with speeds up to  
24 MHz, providing a four MIPS 8-bit Harvard architecture micro-  
SYSTEM RESOURCES  
June 2004  
© Cypress MicroSystems, Inc. 2004 — Document No. 38-12027 Rev. **  
1
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