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CY8C22345H

更新时间: 2024-01-18 03:22:08
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
36页 914K
描述
Automotive PSoC? Programmable System-on-Chip?

CY8C22345H 数据手册

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CY8C21345, CY8C21645  
CY8C22345, CY8C22345H, CY8C22645  
®
Automotive PSoC  
Programmable System-on-Chip™  
Two dedicated clock resources for CapSense  
Two dedicated 16-bit timers/counters for CapSense  
scanning  
Features  
Automotive Electronics Council (AEC) Q100 qualified  
Powerful Harvard-architecture processor  
M8C processor speeds up to 24 MHz  
8 × 8 multiply, 32-bit accumulate  
Low power at high speed  
Automotive A-grade: 3.0 V to 5.25 V operation at –40 °C to  
+85 °C temperature range  
Versatile analog mux  
Common internal analog bus  
Simultaneous connection of I/O combinations  
Programmable pin configurations  
25 mA sink, 10 mA drive on all GPIOs  
Pull-up, pull-down, high Z, strong, or open drain drive modes  
on all GPIOs  
Analog input on all GPIOs  
Configurable interrupt on all GPIOs  
Additional system resources:  
I2C master, slave, or multi-master  
• Operation up to 400 kHz  
• Hardware address detection feature  
Watchdog and sleep timers  
User-configurable low voltage detection  
Integrated supervisory circuit  
Automotive E-grade: 4.75 V to 5.25 V operation at –40 °C to  
+125 °C temperature range  
Advanced peripherals (PSoC® blocks)  
Six analog Type ‘E’ PSoC blocks provide:  
• Up to four comparators with digital-to-analog converters  
(DAC) references  
• Up to 10-bit single or dual analog-to-digital converters  
(ADCs)  
Up to eight digital PSoC blocks provide:  
• 8 to 32-bit timers, counters, and pulse width modulators  
(PWMs)  
On-chip precision voltage reference  
Hardware real time clock (RTC) block  
• One-shot, multi-shot mode in timers and PWMs  
• PWM with deadband in one digital block  
• Shift register, cyclical redundancy check (CRC), and  
pseudo random sequence (PRS) modules  
Block Diagram  
• Full- or half-duplex UARTs  
Port 4 Port 3 Port 2 Port 1 Port 0  
• SPI masters or slaves, 8- to 16-bit variable data length  
• Connectable to all general-purpose I/O (GPIO) pins  
PSoC CORE  
Complex peripherals by combining blocks  
Powerfulsynchronizationsupport,analogmoduleoperations  
can be synchronized by digital blocks or external signals.  
System Bus  
Global Digital  
Global Analog Interconnect  
Interconnect  
High-speed 10-bit successive approximation register (SAR)  
ADC with sample and hold optimized for embedded control  
CY8C22345H devices integrate Immersion® TouchSense®  
SRAM  
SROM Flash 16K/8K  
1KB/512B  
Sleep and  
Watchdog  
CPU Core (M8C)  
Interrupt  
Controller  
haptics technology for ERM drive control  
Precision, programmable clocking  
Internal oscillator up to 24 MHz  
Multiple Clock Sources  
(Includes IMO, ILO, PLL, and ECO)  
High accuracy 24 MHz with optional 32-kHz crystal and  
phase locked loop (PLL)  
Optional external oscillator, up to 24 MHz  
Internal low speed, low-power oscillator for watchdog and  
sleep functionality  
DIGITAL SYSTEM  
ANALOG SYSTEM  
Analog  
Ref  
10-bit SAR  
ADC  
Digital Block  
Array  
Analog  
Input  
Flexible on-chip memory  
Muxing  
Up to 16 KB flash program storage, 1000 erase/write cycles  
Up to 1 KB SRAM data storage  
In-System Serial Programming (ISSP)  
Partial flash updates  
Analog  
Block  
Array  
CapSense Digital  
Resources  
Flexible protection modes  
EEPROM emulation in flash  
Optimized CapSense® resource  
Supports two CapSense channels with simultaneous  
scanning  
Two current DACs provide programmable sensor tuning in  
firmware  
POR and LVD  
System Resets  
Internal  
Voltage  
Ref.  
Digital  
Clocks  
Multiply  
Accum.  
I2C  
RTC  
SYSTEM RESOURCES  
Cypress Semiconductor Corporation  
Document Number: 001-55397 Rev. *I  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 18, 2011  
[+] Feedback  

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