CY8C23433, CY8C23533
PSoC® Programmable System-on-Chip™
Features
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ 8x8 Multiply, 32-Bit Accumulate
■ Complete Development Tools
❐ Free Development Software (PSoC Designer™)
❐ Full-Featured In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Low Power at High Speed
❐ 3.0 to 5.25V Operating Voltage
❐ Complex Breakpoint Structure
❐ Industrial Temperature Range: -40°C to +85°C
❐ 128K Bytes Trace Memory
■ Advanced Peripherals (PSoC Blocks)
❐ 4 Rail-to-Rail analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
Logic Block Diagram
• Up to 8-Bit DACs
Analog
Port 3 Port 2 Port 1 Port 0
Drivers
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐ 4 Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
PSoC CORE
System Bus
• Full-Duplex UART
Global Digital Interconnect
Global Analog Interconnect
• Multiple SPI™ Masters or Slaves
• Connectable to All GPIO Pins
SRAM
256 Bytes
SROM
Flash 8K
❐ Complex Peripherals by Combining Blocks
❐ High-Speed 8-Bit SAR ADC Optimized for Motor Control
Sleep and
Watchdog
CPUCore(M8C)
Interrupt
Controller
■ Precision, Programmable Clocking
❐ Internal ±2.5% 24/48 MHz Oscillator
MultipleClockSources
(IncludesIMO,ILO, PLL, andECO)
❐ High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL
❐ Optional External Oscillator, up to 24 MHz
❐ Internal Oscillator for Watchdog and Sleep
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref
Digital
Block
Array
Analog
■ Flexible On-Chip Memory
Block Array
❐ 8K Bytes Flash Program Storage 50,000 Erase/Write Cycles
❐ 256 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
2 Columns
4 Blocks
1 Row
4 Blocks
Analog
Input
Muxing
SAR8 ADC
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■ Programmable Pin Configurations
❐ 25 mA Sink on all GPIO
❐ Pull up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
❐ Up to Ten Analog Inputs on GPIO
❐ Two 30 mA Analog Outputs on GPIO
❐ Configurable Interrupt on All GPIO
Internal
Voltage
Ref.
Digital
Clocks
Multiply
Accum.
POR and LVD
System Resets
I2C
Decimator
SYSTEM RESOURCES
■ Additional System Resources
❐ I2C™ Slave, Master, and Multi-Master to 400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-chip Precision Voltage Reference
Cypress Semiconductor Corporation
Document Number: 001-44369 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 05, 2008
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