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CY8C21323-24PVXI PDF预览

CY8C21323-24PVXI

更新时间: 2024-11-22 14:53:51
品牌 Logo 应用领域
英飞凌 - INFINEON 时钟微控制器光电二极管
页数 文件大小 规格书
47页 681K
描述
CY8C21x23

CY8C21323-24PVXI 数据手册

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CY8C21123/CY8C21223/CY8C21323  
PSoC® Programmable System-on-Chip™  
Features  
Powerful Harvard-architecture processor:  
M8C processor speeds up to 24 MHz  
Low power at high speed  
Additional system resources:  
I2C master, slave and multi-master to 400 kHz  
Watchdog and sleep timers  
Operating voltage: 2.4 V to 5.25 V  
User-configurable low-voltage detection (LVD)  
Operating voltages down to 1.0 V using on-chip switch mode  
pump (SMP)  
Integrated supervisory circuit  
On-chip precision voltage reference  
Industrial temperature range: –40 °C to +85 °C  
Advanced peripherals (PSoC® blocks):  
Four analog type “E” PSoC blocks provide:  
• Two comparators with digital to analog converter (DAC)  
references  
Logic Block Diagram  
Port 1 Port 0  
• Single or dual 10-Bit 8-to-1 analog to digital converter  
(ADC)  
Four digital PSoC blocks provide:  
• 8- to 32-bit timers and counters, 8- and 16-bit pulse-width  
modulators (PWMs)  
PSoC  
CORE  
SystemBus  
• CRC and PRS modules  
Global Digital Interconnect  
Full duplex UART, SPImaster or slave: Connectable to all  
Global Analog Interconnect  
Flash  
CPUCore  
general-purpose I/O (GPIO) pins  
Complex peripherals by combining blocks  
SROM  
SRAM  
Flexible on-chip memory:  
Sleep and  
Watchdog  
Interrupt  
Controller  
(M8C)  
4 KB flash program storage 50,000 erase/write cycles  
256 bytes SRAM data storage  
In-system serial programming (ISSP)  
Partial flash updates  
Clock Sources  
(Includes IMO and ILO)  
Flexible protection modes  
EEPROM emulation in flash  
DIGITAL SYSTEM  
ANALOG SYSTEM  
Analog  
Ref .  
Complete development tools:  
Digital  
PSoC Block  
Array  
Analog  
PSoC Block  
Array  
Free development software (PSoC Designer™)  
Full-featured, in-circuit emulator (ICE) and programmer  
Full-speed emulation  
Complex breakpoint structure  
128-KB trace memory  
Precision, programmable clocking:  
Internal ±5% 24- / 48-MHz main oscillator  
Internal low-speed, low-power oscillator for watchdog and  
sleep functionality  
Sw itch  
Mode  
Pump  
POR and LVD  
System Resets  
Internal  
Voltage  
Ref .  
Digital  
Clocks  
I2C  
Programmable pin configurations:  
25-mA sink, 10-mA source on all GPIOs  
SYSTEM RESOURCES  
Pull-up, pull-down, high Z, strong, or open-drain drive modes  
on all GPIOs  
Up to eight analog inputs on all GPIOs  
Configurable interrupt on all GPIOs  
Errata: When the device is operated within 0 °C to 70 °C, the frequency tolerance is reduced to ±2.5%, but if operated at extreme temperature (below 0 °C or above 70 °C),  
frequency tolerance deviates from ±2.5% to ±5%. For information on silicon errata, see “Errata” on page 43.  
Cypress Semiconductor Corporation  
Document Number: 38-12022 Rev. AC  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised November 22, 2017  

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