CY8C20XX6A/S
Document History Page (continued)
DocumentTitle:CY8C20XX6A/S, 1.8VProgrammableCapSense® ControllerwithSmartSense™Auto-tuning1–33Buttons,
0–6 Sliders
Document Number: 001-54459
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
*G
3247491 TTO/JPM/
ARVM / BVI
06/16/11
Add 4 new parameters to Table 14 on page 21, and 2 new parameters to Table
15 on page 22.
Changed Typ values for the following parameters: I
I
I
V
DD24, DD12, DD6, OSLPC.
Added footnote # 40 and referred it to pin numbers 1, 14, 15, 42, and 43 under
Table 10 on page 18.
Added footnote # 43 and referred it to parameter V
under Table 11 on page 19.
IOZ
Added “t
” parameter to Table 27 on page 27.
JIT_IMO
Included footnote # 59 and added reference to t
27 on page 27.
specification under Table
JIT_IMO
Updated Solder Reflow Specifications on page 37 as per specs 25-00090 and
25-00103.
I
Max value changed from 0.5 µA to 1.1 µA in Table 13 on page 20.
SB0
Added Table 26 on page 26.
Updated part numbers for “SmartSense_EMC” enabled CapSense controller.
”
*H
*I
3367332
3371807
BTK /
SSHH /
JPM/TTO/
VMAD
09/09/11
Added parameter “t
Added parameter “I
to Table 27 on page 27.
” to Table 13 on page 20.
OS
SBI2C
Added Table 24 on page 26.
Added Table 25 on page 26.
Replaced text “Port 2 or 3 pins” with “Port 2 or 3 or 4 pins” in Table 14, Table 15,
Table 16, and Table 28.
MATT
09/30/2011 Updated Packaging Information (Updated the next revision package outline for
Figure 20, Figure 23 and included a new package outline Figure 25).
Updated Ordering Information (Added new part numbers
CY8C20636A-24LQXI, CY8C20636A-24LQXIT, CY8C20646A-24LQXI,
CY8C20646A-24LQXIT, CY8C20666A-24LQXI, CY8C20666A-24LQXIT,
CY8C20666AS-24LQXI, CY8C20666AS-24LQXIT, CY8C20646AS-24LQXI
and CY8C20646AS-24LQXIT).
Updated in new template.
*J
3401666
3414479
MATT
KPOL
10/11/2011 No technical updates.
*K
10/19/2011 Removed clock stretching feature on page 1.
2
Removed I C enhanced slave interface point from Additional System
Resources.
*L
3452591 BVI / UDYG 12/01/2011 Changed document title.
Updated DC Chip-Level Specifications table.
Updated Solder Reflow Specifications section.
Updated Getting Started and Designing with PSoC Designer sections.
Included Development Tools section.
Updated Software under Development Tool Selection section.
*M
*N
3473330
3587003
ANBA
DST
12/22/2011 Updated DC Chip-Level Specifications under Electrical Specifications (updated
maximum value of I
parameter from 1.1 µA to 1.05 µA).
SB0
04/16/2012 Added note for WLCSP package on page 1.
Added Sensing inputs to pin table captions.
Updated Conditions for DC Reference Buffer Specifications.
Updated t
Added note for t
description in AC Chip-Level Specifications.
JIT_IMO
, t
, t
, and t
specs.
VDDWAIT VDDXRES ACQ
XRESINI
Removed WLCSP package outline.
*O
3638569
BVI
06/06/2012 Updated F
parameter in the Table 36, “SPI Slave AC Specifications,” on
SCLK
page 33.
Changed t
page 32.
to t
in Table 35, “SPI Master AC Specifications,” on
OUT_H
OUT_HIGH
Updated package diagram 001-57280 to *C revision.
Document Number: 001-54459 Rev. *T
Page 49 of 51