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CY8C20334-12LKXI PDF预览

CY8C20334-12LKXI

更新时间: 2024-11-24 20:00:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟微控制器
页数 文件大小 规格书
38页 696K
描述
Multifunction Peripheral, CMOS, 4 X 4 MM, 0.60 MM HEIGHT, LEAD FREE, MO-220, QFN-16

CY8C20334-12LKXI 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:QFN包装说明:HVQCCN, LCC24,.16SQ,20
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.72
地址总线宽度:位大小:8
边界扫描:NO总线兼容性:USB
CPU系列:M8C最大时钟频率:12 MHz
外部数据总线宽度:JESD-30 代码:S-XQCC-N24
JESD-609代码:e3长度:4 mm
湿度敏感等级:3端子数量:24
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC24,.16SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:2.7/5 V认证状态:Not Qualified
RAM(字节):512RAM(字数):512
ROM(单词):8192ROM可编程性:FLASH
座面最大高度:0.6 mm速度:12 MHz
子类别:Microcontrollers最大压摆率:2.5 mA
最大供电电压:5.25 V最小供电电压:2.4 V
标称供电电压:3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:4 mm
Base Number Matches:1

CY8C20334-12LKXI 数据手册

 浏览型号CY8C20334-12LKXI的Datasheet PDF文件第2页浏览型号CY8C20334-12LKXI的Datasheet PDF文件第3页浏览型号CY8C20334-12LKXI的Datasheet PDF文件第4页浏览型号CY8C20334-12LKXI的Datasheet PDF文件第5页浏览型号CY8C20334-12LKXI的Datasheet PDF文件第6页浏览型号CY8C20334-12LKXI的Datasheet PDF文件第7页 
CY8C20234, CY8C20334  
CY8C20434, CY8C20534, CY8C20634  
PSoC® Programmable System-on-Chip  
Features  
Low Power CapSense® Block  
Additional System Resources  
Configurable Capacitive Sensing Elements  
Supports Combination of CapSense Buttons, Sliders, Touch-  
pads, and Proximity Sensors  
Configurable Communication Speeds  
• I2C: Selectable to 50 kHz, 100 kHz, or 400 kHz  
• SPI: Configurable between 46.9 kHz and 3 MHz  
I2C Slave  
Powerful Harvard Architecture Processor  
M8C Processor Speeds Running up to 12 MHz  
Low Power at High Speed  
SPI Master and SPI Slave  
Watchdog and Sleep Timers  
Internal Voltage Reference  
2.4V to 5.25V Operating Voltage  
Integrated Supervisory Circuit  
Industrial Temperature Range: -40°C to +85°C  
Flexible On-Chip Memory  
8K Flash Program Storage  
50,000 Erase/Write Cycles  
Logic Block Diagram  
512 Bytes SRAM Data Storage  
Partial Flash Updates  
Flexible Protection Modes  
Interrupt Controller  
Port 3 Port 2 Port 1 Port 0 Config LDO  
PSoC  
CORE  
System Bus  
In-System Serial Programming (ISSP)  
Complete Development Tools  
Free Development Tool (PSoC Designer™)  
Full Featured, In-Circuit Emulator, and Programmer  
Full Speed Emulation  
Complex Breakpoint Structure  
128K Trace Memory  
Global Analog Interconnect  
SRAM  
512 Bytes  
SROM  
Flash 8K  
CPU Core  
(M8C)  
Sleep and  
Watchdog  
Interrupt  
Controller  
6/12 MHz Internal Main Oscillator  
Precision, Programmable Clocking  
Internal ±5.0% 6/12 MHz Main Oscillator  
Internal Low Speed Oscillator at 32 kHz for Watchdog and  
Sleep  
Analog  
Ref.  
ANALOG  
SYSTEM  
CapSense  
Block  
Programmable Pin Configurations  
Pull Up, High Z, Open Drain, and CMOS Drive Modes on All  
GPIO  
Up to 28 Analog Inputs on GPIO  
Configurable Inputs on All GPIO  
Selectable, Regulated Digital I/O on Port 1  
• 3.0V, 20 mA Total Port 1 Source Current  
• 5 mA Strong Drive Mode on Port 1 Versatile Analog Mux  
Common Internal Analog Bus  
Simultaneous Connection of I/O Combinations  
Comparator Noise Immunity  
POR and LVD  
System Resets  
I2C Slave/SPI  
Master-Slave  
Analog  
Mux  
SYSTEM RESOURCES  
Low Dropout Voltage Regulator for the Analog Array  
Cypress Semiconductor Corporation  
Document Number: 001-05356 Rev. *I  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised September 25, 2009  
[+] Feedback  

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