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CY7C65620-56LTXI

更新时间： 2024-11-25 11:14:11
品牌 Logo 应用领域
英飞凌 - INFINEON 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟PC外围集成电路
页数 文件大小 规格书
32页 669K
描述
2 port Single-TT hub (Configurable with GPIOs, LED indicator and EEPROM) with 56-pin QFN 2-Port QFN Bulk, I-grade

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CY7C65620-56LTXI 数据手册

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CY7C65620  
CY7C65630  
EZ-USB HX2LP™  
Low Power USB 2.0 Hub Controller Family  
EZ-USB HX2LP™ Low Power USB 2.0 Hub Controller Family  
■ Integrated upstream and downstream termination resistors  
■ Integrated port status indicator control  
Features  
■ USB 2.0 hub controller  
■ 24 MHz external crystal (integrated phase-locked loop (PLL))  
■ Automotive and Industrial grade option (–40 °C to 85 °C)  
■ Compliant with USB 2.0 specification  
■ USB-IF certified: TID# 30000009  
■ In-system EEPROM programming  
■ Configurable with external SPI EEPROM:  
❐ Vendor ID, Product ID, Device ID (VID/PID/DID)  
❐ Number of active ports  
❐ Number of removable ports  
❐ Maximum power setting for high-speed and full-speed  
❐ Hub controller power setting  
❐ Power-on timer  
■ Windows Hardware Quality Lab (WHQL) Compliant  
■ Up to four downstream ports supported  
■ Supports bus powered and self powered modes  
■ Single transaction translator (TT)  
❐ Overcurrent detection mode  
❐ Enabled and disabled overcurrent timer  
❐ Overcurrent pin polarity  
■ Bus power configurations  
■ Fit, form, and function compatible with CY7C65640 and  
CY7C65640A (TetraHub™)  
❐ Indicator pin polarity  
❐ Compound device  
❐ Enable full-speed only  
■ Space saving 56-pin QFN  
■ Single power supply requirement  
❐ Internal regulator for reduced cost  
❐ Disable port indicators  
❐ Ganged power switching  
❐ Self and bus powered compatibility  
❐ Fully configurable string descriptors for multiple language  
support  
■ Integrated upstream pull-up resistor  
■ Integrated pull-down resistors for all downstream ports  
For a complete list of related documentation, click here.  
Block Diagram –  
CY7C65630  
D+  
D -  
High-Speed  
USB Control Logic  
USB 2.0 PHY  
PLL  
Serial  
Interface  
Engine  
24 MHz  
Crystal  
SPI_SCK  
SPI_SD  
SPI_CS  
SPI Communication  
Block  
USB Upstream Port  
Transaction Translator  
TT RAM  
Hub Repeater  
Routing Logic  
USB Downstream Port 1  
USB Downstream Port 2  
USB Downstream Port 3  
USB Downstream Port 4  
USB 2.0  
PHY  
Port  
Status  
Port Power  
Control  
USB 2.0 Port Power  
PHY  
Control  
Port  
Status  
USB 2.0 Port Power  
PHY  
Control  
Port  
Status  
USB 2.0 Port Power  
PHY  
Control  
Port  
Status  
D+ D- PWR#[4]  
LED  
D+ D- PWR#[3]  
OVR#[3]  
LED  
D+ D- PWR#[1]  
OVR#[1]  
LED D+ D- PWR#[2]  
LED  
OVR#[2]  
OVR#[4]  
Errata: For information on silicon errata, see “Errata” on page 28. Details include trigger conditions, devices affected, and proposed workaround.  
Cypress Semiconductor Corporation  
Document Number: 38-08037 Rev. AE  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised June 8, 2017  
1234567...32

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