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CY7C65630-56LTXIT PDF预览

CY7C65630-56LTXIT

更新时间: 2024-11-27 12:22:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 控制器
页数 文件大小 规格书
28页 395K
描述
EZ-USB HX2LP™ Low Power USB 2.0 Hub Controller Family

CY7C65630-56LTXIT 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:QFN包装说明:QFN-56
针数:56Reach Compliance Code:compliant
ECCN代码:5A991.B.4.BHTS代码:8542.31.00.01
风险等级:5.8最大时钟频率:24 MHz
JESD-30 代码:S-XQCC-N56JESD-609代码:e4
长度:8 mm湿度敏感等级:3
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC56,.31SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1 mm
子类别:Bus Controllers最大压摆率:260 mA
最大供电电压:3.45 V最小供电电压:3.15 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:8 mm
uPs/uCs/外围集成电路类型:BUS CONTROLLER, UNIVERSAL SERIAL BUS

CY7C65630-56LTXIT 数据手册

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CY7C65620/CY7C65630  
EZ-USB HX2LP™  
Low Power USB 2.0 Hub Controller Family  
EZ-USB HX2LP™ Low Power USB 2.0 Hub Controller Family  
Integrated upstream and downstream termination resistors  
Integrated port status indicator control  
Features  
USB 2.0 hub controller  
24 MHz external crystal (integrated phase-locked loop (PLL))  
Automotive and Industrial grade option (–40 °C to 85 °C)  
Compliant with USB 2.0 specification  
USB-IF certified: TID# 30000009  
In-system EEPROM programming  
Configurable with external SPI EEPROM:  
Vendor ID, Product ID, Device ID (VID/PID/DID)  
Number of active ports  
Number of removable ports  
Maximum power setting for high-speed and full-speed  
Hub controller power setting  
Power-on timer  
Windows Hardware Quality Lab (WHQL) Compliant  
Up to four downstream ports supported  
Supports bus powered and self powered modes  
Single transaction translator (TT)  
Overcurrent detection mode  
Enabled and disabled overcurrent timer  
Overcurrent pin polarity  
Bus power configurations  
Fit, form, and function compatible with CY7C65640 and  
CY7C65640A (TetraHub™)  
Indicator pin polarity  
Compound device  
Enable full-speed only  
Space saving 56-pin QFN  
Single power supply requirement  
Internal regulator for reduced cost  
Disable port indicators  
Ganged power switching  
Self and bus powered compatibility  
Fully configurable string descriptors for multiple language  
support  
Integrated upstream pull-up resistor  
Integrated pull-down resistors for all downstream ports  
Block Diagram CY7C65630  
D+  
D -  
High-Speed  
USB Control Logic  
USB 2.0 PHY  
PLL  
Serial  
Interface  
Engine  
24 MHz  
Crystal  
SPI_SCK  
SPI_SD  
SPI Communication  
Block  
SPI_CS  
USB Upstream Port  
Transaction Translator  
TT RAM  
Hub Repeater  
Routing Logic  
USB Downstream Port 1  
USB Downstream Port 2  
USB Downstream Port 3  
USB Downstream Port 4  
USB 2.0  
PHY  
Port  
Status  
Port Power  
Control  
USB 2.0 Port Power  
PHY  
Control  
Port  
Status  
USB 2.0 Port Power  
PHY  
Control  
Port  
Status  
USB 2.0 Port Power  
PHY  
Control  
Port  
Status  
D+ D- PWR#[4]  
LED  
D+ D- PWR#[3]  
OVR#[3]  
LED  
D+ D- PWR#[1]  
OVR#[1]  
LED D+ D- PWR#[2]  
LED  
OVR#[2]  
OVR#[4]  
Cypress Semiconductor Corporation  
Document Number: 38-08037 Rev. *V  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised September 6, 2012  

CY7C65630-56LTXIT 替代型号

型号 品牌 替代类型 描述 数据表
CY7C65630-56LTXI CYPRESS

完全替代

EZ-USB HX2LP™ Low Power USB 2.0 Hub Control

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