Datasheet > 存储 > FIFO> CY7C443-20JC

CY7C443-20JC

更新时间： 2024-11-24 04:10:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片
页数	文件大小	规格书
15页	220K
描述
Clocked 512 x 9, 2K x 9 FIFOs

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

CY7C443-20JC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFJ	包装说明：	PLASTIC, LCC-32
针数：	32	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.71
风险等级：	8.74	最长访问时间：	15 ns
其他特性：	PARITY GENERATOR/CHECKER	最大时钟频率 (fCLK)：	50 MHz
周期时间：	20 ns	JESD-30 代码：	R-PQCC-J32
JESD-609代码：	e0	长度：	13.97 mm
内存密度：	18432 bit	内存集成电路类型：	OTHER FIFO
内存宽度：	9	功能数量：	1
端子数量：	32	字数：	2048 words
字数代码：	2000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	2KX9	输出特性：	TOTEM POLE
可输出：	NO	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装等效代码：	LDCC32,.5X.6
封装形状：	RECTANGULAR	封装形式：	CHIP CARRIER
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V	认证状态：	Not Qualified
座面最大高度：	3.55 mm	最大待机电流：	0.03 A
子类别：	FIFOs	最大压摆率：	0.12 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	11.43 mm

CY7C443-20JC 数据手册

CY7C441

CY7C443

Clocked 512 x 9, 2K x 9 FIFOs

lutions for a wide variety of data buffering needs, including

high-speed data acquisition, multiprocessor interfaces, and

communications buffering.

Features

• High-speed, low-power, first-in first-out (FIFO)

memories

Both FIFOs have 9-bit input and output ports that are con-

trolled by separate clock and enable signals. The input port is

controlled by a free-running clock (CKW) and a write enable

pin (ENW). When ENW is asserted, data is written into the

FIFO on the rising edge of the CKW signal. While ENW is held

active, data is continually written into the FIFO on each CKW

cycle. The output port is controlled in a similar manner by a

free-running read clock (CKR) and a read enable pin (ENR).

The read (CKR) and write (CKW) clocks may be tied together

for single-clock operation or the two clocks may be run inde-

pendently for asynchronous read/write applications. Clock fre-

quencies up to 83.3 MHz are acceptable.

• 512 x 9 (CY7C441)

• 2,048 x 9 (CY7C443)

• 0.65 micron CMOS for optimum speed/power

• High-speed 83-MHz operation (12 ns read/write cycle

time)

• Low power — I_CC=70 mA

• Fully asynchronous and simultaneous read and write

operation

• Empty, Almost Empty, and Almost Full status flags

• TTL compatible

• Parity generation/checking

The CY7C441 and CY7C443 clocked FIFOs provide two sta-

tus flag pins (F1 and F2). These flags are decoded to deter-

mine one of four states: Empty, Almost Empty, Intermediate,

and Almost Full (Table 1). The flags are synchronous; i.e.,

change state relative to either the read clock (CKR) or the write

clock (CKW). The Empty and Almost Empty states are updat-

ed exclusively by the CKR while Almost Full is updated exclu-

sively by CKW. The synchronous flag architecture guarantees

that the flags maintain their status for some minimum time.

• Independent read and write enable pins

• Supports free-running 50% duty cycle clock inputs

• Center power and ground pins for reduced noise

• Width Expansion Capability

• Available in PLCC packages

Functional Description

The CY7C441 and CY7C443 are high-speed, low-power,

first-in first-out (FIFO) memories with clocked read and write

interfaces. Both FIFOs are 9 bits wide. The CY7C441 has a

512 word by 9 bit memory array, while the CY7C443 has a

2048 word by 9 bit memory array. These devices provide so-

The CY7C441 and the CY7C443 use center power and

ground for reduced noise. Both configurations are fabricated

using an advanced.65µm CMOS technology. Input ESD pro-

tection is greater than 2001V, and latch-up is prevented by

reliable layout techniques and guard rings.

Logic Block Diagram

Pin Configuration

CKW

ENW

0– 8

PLCC

Top View

INPUT

NCD

32 31 30

FLAG

LOGIC

WRITE

CONTROL

LOGIC

ENW

CKW

7C441

7C443

CKR

ENR

RAM

ARRAY

512x 9

2048x 9

WRITE

POINTER

READ

POINTER

14 15 16 17 1819 20

RESET

LOGIC

READ

CONTROL

LOGIC

C441-2

Q Q NC Q

Q Q

5 6

OUTPUT

CKR

ENR

C441-1

0– 8

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-06032 Rev. *A

Revised December 26, 2002

12 3 4 5 6 7...15

中文翻译

下载PDF

与CY7C443-20JC相关器件

型号	品牌	获取价格	描述	数据表
CY7C443-20JCR	CYPRESS	获取价格	FIFO, 2KX9, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C443-20JCT	CYPRESS	获取价格	FIFO, 2KX9, 15ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C443-20JI	CYPRESS	获取价格	Clocked 512 x 9, 2K x 9 FIFOs
CY7C443-20JIT	CYPRESS	获取价格	FIFO, 2KX9, 15ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C443-20KMB	ETC	获取价格	x9 Synchronous FIFO
CY7C443-20LC	ETC	获取价格	x9 Synchronous FIFO
CY7C443-20LMB	CYPRESS	获取价格	FIFO, 2KX9, 15ns, Synchronous, CMOS, CQCC32, CERAMIC, LCC-32
CY7C443-20PC	CYPRESS	获取价格	FIFO, 2KX9, 15ns, Synchronous, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28
CY7C443-20VCR	CYPRESS	获取价格	FIFO, 2KX9, Synchronous, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28
CY7C443-20VCT	CYPRESS	获取价格	FIFO, 2KX9, Synchronous, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28

与CY7C443-20JC相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

39
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

31
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

59
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

55

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C443-20JC

CY7C443-20JC 技术参数

CY7C443-20JC 数据手册

与CY7C443-20JC相关器件

与CY7C443-20JC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C443-20JC

CY7C443-20JC 技术参数

CY7C443-20JC 数据手册

与CY7C443-20JC相关器件

与CY7C443-20JC相关文章

您还可以找

您在本页遇到什么问题？