Datasheet > 存储 > FIFO> CY7C443-20LMB

CY7C443-20LMB

更新时间： 2024-11-27 13:07:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片
页数	文件大小	规格书
15页	220K
描述
FIFO, 2KX9, 15ns, Synchronous, CMOS, CQCC32, CERAMIC, LCC-32

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技术参数
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CY7C443-20LMB 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFJ
包装说明：	CERAMIC, LCC-32	针数：	32
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.89
Is Samacsys：	N	最长访问时间：	15 ns
最大时钟频率 (fCLK)：	50 MHz	周期时间：	20 ns
JESD-30 代码：	R-CQCC-N32	JESD-609代码：	e0
长度：	13.97 mm	内存密度：	18432 bit
内存集成电路类型：	OTHER FIFO	内存宽度：	9
功能数量：	1	端子数量：	32
字数：	2048 words	字数代码：	2000
工作模式：	SYNCHRONOUS	最高工作温度：	125 °C
最低工作温度：	-55 °C	组织：	2KX9
输出特性：	TOTEM POLE	可输出：	NO
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	QCCN
封装等效代码：	LCC32,.45X.55	封装形状：	RECTANGULAR
封装形式：	CHIP CARRIER	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	5 V
认证状态：	Not Qualified	筛选级别：	38535Q/M;38534H;883B
座面最大高度：	2.286 mm	最大待机电流：	0.16 A
子类别：	FIFOs	最大压摆率：	0.16 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	NO LEAD
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	11.43 mm
Base Number Matches：	1

CY7C443-20LMB 数据手册

CY7C441

CY7C443

Clocked 512 x 9, 2K x 9 FIFOs

lutions for a wide variety of data buffering needs, including

high-speed data acquisition, multiprocessor interfaces, and

communications buffering.

Features

• High-speed, low-power, first-in first-out (FIFO)

memories

Both FIFOs have 9-bit input and output ports that are con-

trolled by separate clock and enable signals. The input port is

controlled by a free-running clock (CKW) and a write enable

pin (ENW). When ENW is asserted, data is written into the

FIFO on the rising edge of the CKW signal. While ENW is held

active, data is continually written into the FIFO on each CKW

cycle. The output port is controlled in a similar manner by a

free-running read clock (CKR) and a read enable pin (ENR).

The read (CKR) and write (CKW) clocks may be tied together

for single-clock operation or the two clocks may be run inde-

pendently for asynchronous read/write applications. Clock fre-

quencies up to 83.3 MHz are acceptable.

• 512 x 9 (CY7C441)

• 2,048 x 9 (CY7C443)

• 0.65 micron CMOS for optimum speed/power

• High-speed 83-MHz operation (12 ns read/write cycle

time)

• Low power — I_CC=70 mA

• Fully asynchronous and simultaneous read and write

operation

• Empty, Almost Empty, and Almost Full status flags

• TTL compatible

• Parity generation/checking

The CY7C441 and CY7C443 clocked FIFOs provide two sta-

tus flag pins (F1 and F2). These flags are decoded to deter-

mine one of four states: Empty, Almost Empty, Intermediate,

and Almost Full (Table 1). The flags are synchronous; i.e.,

change state relative to either the read clock (CKR) or the write

clock (CKW). The Empty and Almost Empty states are updat-

ed exclusively by the CKR while Almost Full is updated exclu-

sively by CKW. The synchronous flag architecture guarantees

that the flags maintain their status for some minimum time.

• Independent read and write enable pins

• Supports free-running 50% duty cycle clock inputs

• Center power and ground pins for reduced noise

• Width Expansion Capability

• Available in PLCC packages

Functional Description

The CY7C441 and CY7C443 are high-speed, low-power,

first-in first-out (FIFO) memories with clocked read and write

interfaces. Both FIFOs are 9 bits wide. The CY7C441 has a

512 word by 9 bit memory array, while the CY7C443 has a

2048 word by 9 bit memory array. These devices provide so-

The CY7C441 and the CY7C443 use center power and

ground for reduced noise. Both configurations are fabricated

using an advanced.65µm CMOS technology. Input ESD pro-

tection is greater than 2001V, and latch-up is prevented by

reliable layout techniques and guard rings.

Logic Block Diagram

Pin Configuration

CKW

ENW

0– 8

PLCC

Top View

INPUT

NCD

32 31 30

FLAG

LOGIC

WRITE

CONTROL

LOGIC

ENW

CKW

7C441

7C443

CKR

ENR

RAM

ARRAY

512x 9

2048x 9

WRITE

POINTER

READ

POINTER

14 15 16 17 1819 20

RESET

LOGIC

READ

CONTROL

LOGIC

C441-2

Q Q NC Q

Q Q

5 6

OUTPUT

CKR

ENR

C441-1

0– 8

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-06032 Rev. *A

Revised December 26, 2002

12 3 4 5 6 7...15

中文翻译

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与CY7C443-20LMB相关器件

型号	品牌	获取价格	描述	数据表
CY7C443-20PC	CYPRESS	获取价格	FIFO, 2KX9, 15ns, Synchronous, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28
CY7C443-20VCR	CYPRESS	获取价格	FIFO, 2KX9, Synchronous, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28
CY7C443-20VCT	CYPRESS	获取价格	FIFO, 2KX9, Synchronous, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28
CY7C443-30DC	ETC	获取价格	x9 Synchronous FIFO
CY7C443-30DI	ETC	获取价格	x9 Synchronous FIFO
CY7C443-30JC	CYPRESS	获取价格	Clocked 512 x 9, 2K x 9 FIFOs
CY7C443-30JCR	CYPRESS	获取价格	FIFO, 2KX9, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C443-30JCT	CYPRESS	获取价格	FIFO, 2KX9, 20ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C443-30JI	CYPRESS	获取价格	Clocked 512 x 9, 2K x 9 FIFOs
CY7C443-30JIT	CYPRESS	获取价格	FIFO, 2KX9, 20ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32

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