Datasheet > 存储 > FIFO> CY7C43684-15AI

CY7C43684-15AI

更新时间： 2024-02-06 03:29:17

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路先进先出芯片时钟
页数	文件大小	规格书
39页	646K
描述
1K/4K x36 x2 Bidirectional Synchronous FIFO with Bus Matching

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CY7C43684-15AI 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-128
针数：	128	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.71
风险等级：	5.88	Is Samacsys：	N
最长访问时间：	10 ns	其他特性：	MAILBOX
最大时钟频率 (fCLK)：	67 MHz	周期时间：	15 ns
JESD-30 代码：	R-PQFP-G128	JESD-609代码：	e0
长度：	20 mm	内存密度：	589824 bit
内存集成电路类型：	BI-DIRECTIONAL FIFO	内存宽度：	36
功能数量：	1	端子数量：	128
字数：	16384 words	字数代码：	16000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	16KX36
可输出：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装等效代码：	QFP128,.63X.87,20
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	240
电源：	5 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大待机电流：	0.01 A
子类别：	FIFOs	最大压摆率：	0.1 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	TIN LEAD	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	14 mm
Base Number Matches：	1

CY7C43684-15AI 数据手册

CY7C43644

CY7C43664

CY7C43684

Pin Definitions (continued)

Signal Name Description I/O

Function

B_0–35

Port B Data

I/O 36-bit bidirectional data port for side B.

BE/FWFT

Big

This is a dual-purpose pin. During Master Reset, a HIGH on BE will select Big Endian

operation. In this case, depending on the bus size, the most significant byte or word on

Port A is transferred to Port B first for A-to-B data flow. For data flowing from Port B to

Port A the first word/byte written to Port B will come out as the most significant word/byte

on Port A. A LOW on BE will select Little Endian operation. In this case, the least signif-

icant byte or word on Port A is transferred to Port B first for A-to-B data flow. Similarly,

the fist word/byte written into Port B will come out as the least significant word/byte on

Port A for B-to-A data flow. After Master Reset, this pin selects the timing mode. A HIGH

on FWFT selects CY Standard mode, a LOW selects First-Word Fall-Through mode.

Once the timing mode has been selected, the level on this pin must be static throughout

device operation.

Endian/First-

Word Fall-

Through

Select

Bus Match

Select (Port

A HIGH on this pin enables either byte or word bus width on Port B, depending on

the state of SIZE. A LOW selects long-word operation. BM works with SIZE and BE to

select the bus size and endian arrangement for Port B. The level of BM must be static

throughout device operation.

CLKA

CLKB

Port A Clock

Port B Clock

CLKA is a continuous clock that synchronizes all data transfers through Port A and

can be asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all

synchronized to the LOW-to-HIGH transition of CLKA.

CLKB is a continuous clock that synchronizes all data transfers through Port B and

can be asynchronous or coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are all

synchronized to the LOW-to-HIGH transition of CLKB.

CSA

Port A Chip

Select

CSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write on

Port A. The A_0–35outputs are in the high-impedance state when CSA is HIGH.

CSB

Port B Chip

Select

CSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write on

Port B. The B_0–35outputs are in the high-impedance state when CSB is HIGH.

EFA/ORA

Port A Empty/

OutputReady

Flag

This is a dual-function pin. In the CY Standard mode, the EFA function is selected.

EFA indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA

function is selected. ORA indicates the presence of valid data on A_0–35outputs, available

for reading. EFA/ORA is synchronized to the LOW-to-HIGH transition of CLKA.^[1]

EFB/ORB

Port B Empty/

OutputReady

Flag

This is a dual-function pin. In the CY Standard mode, the EFB function is selected.

EFB indicates whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB

function is selected. ORB indicates the presence of valid data on B_0–35outputs, available

for reading. EFB/ORB is synchronized to the LOW-to-HIGH transition of CLKB.^[1]

ENA

Port A Enable

Port B Enable

ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data

on Port A.

ENB

ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data

on Port B.

FFA/IRA

Port A

Full/Input

Ready Flag

This is a dual-function pin. In the CY Standard mode, the FFA function is selected. FFA

indicates whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function

is selected. IRA indicates whether or not there is space available for writing to the FIFO1

memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA.

FFB/IRB

Port B

Full/Input

Ready Flag

This is a dual-function pin. In the CY Standard mode, the FFB function is selected. FFB

indicates whether or not the FIFO2 memory is full. In the FWFT mode, the IRB function

is selected. IRB indicates whether or not there is space available for writing to the FIFO2

memory. FFB/IRB is synchronized to the LOW-to-HIGH transition of CLKB.

Document #: 38-06022 Rev. *B

Page 4 of 39

1 2 345 6 7...39

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CY7C43684AV-10AI	CYPRESS	3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO with Bus Matching	获取价格
CY7C43684AV-15AC	CYPRESS	3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO with Bus Matching	获取价格
CY7C43684AV-15AI	CYPRESS	Bi-Directional FIFO, 16KX36, 10ns, Synchronous, CMOS, PQFP128, 14 X 20 MM, 1.40 MM HEIGHT,	获取价格

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