Datasheet > 存储 > FIFO> CY7C4265A-15ASI

CY7C4265A-15ASI

更新时间： 2024-01-20 04:39:34

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路先进先出芯片时钟
页数	文件大小	规格书
23页	625K
描述
8K/16K x 18 Deep Sync FIFOs

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技术参数
数据手册

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CY7C4265A-15ASI 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, STQFP-64	针数：	64
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.72
Is Samacsys：	N	最长访问时间：	10 ns
其他特性：	RETRANSMIT	最大时钟频率 (fCLK)：	66.7 MHz
周期时间：	15 ns	JESD-30 代码：	S-PQFP-G64
JESD-609代码：	e0	长度：	10 mm
内存密度：	294912 bit	内存集成电路类型：	OTHER FIFO
内存宽度：	18	功能数量：	1
端子数量：	64	字数：	16384 words
字数代码：	16000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	16KX18	可输出：	YES
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装等效代码：	QFP64,.47SQ,20	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	240	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大待机电流：	0.015 A	子类别：	FIFOs
最大压摆率：	0.05 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	TIN LEAD
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	10 mm	Base Number Matches：	1

CY7C4265A-15ASI 数据手册

CY7C4255, CY7C4265, CY7C4265A

8K/16K x 18 Deep Sync FIFOs

Features

Functional Description

The CY7C4255/65/65A are high speed, low power, first-in

first-out (FIFO) memories with clocked read and write interfaces.

All are 18 bits wide and are pin/functionally compatible to the

CY7C42X5 Synchronous FIFO family. The CY7C4255/65/65A

can be cascaded to increase FIFO depth. Programmable

features include Almost Full/Almost Empty flags. These FIFOs

provide solutions for a wide variety of data buffering needs, including

high speed data acquisition, multiprocessor interfaces, and communi-

cations buffering.

■ High Speed, Low Power, First-In First-Out (FIFO) Memories

❐ 8K x 18 (CY7C4255)

❐ 16K x 18 (CY7C4265/4265A)^[1]

■ 0.5 Micron CMOS for Optimum Speed and Power

■ High Speed 100 MHz Operation (10 ns read/write cycle times)

■ Low Power — I_CC= 45 mA

■ Fully Asynchronous and Simultaneous Read and Write

Operation

These FIFOs have 18-bit input and output ports that are

controlled by separate clock and enable signals. The input port

is controlled by a free running Clock (WCLK) and a Write Enable

pin (WEN).When WENis asserted, data is written into the FIFO on the

risingedgeofthe WCLK signal. While WEN is held active, datais contin-

ually written into the FIFO on each cycle. The output port is controlled in

a similar manner by a free-running Read Clock (RCLK) and a Read

Enable pin (REN).Inaddition,theCY7C4255/65/65A haveanOutput

Enable pin (OE). The read and write clocks may be tied together for

single-clock operation or the two clocks may be run independently for

asynchronous read/write applications. Clock frequencies up to

100 MHz are achievable.

■ Empty, Full, Half Full, and Programmable Almost Empty and

Almost Full Status Flags

■ TTL compatible

■ Retransmit Function

■ Output Enable (OE) Pins

■ Independent Read and Write Enable Pins

■ Center Power and Ground Pins for Reduced Noise

■ Supports Free-running 50 percent Duty Cycle Clock Inputs

■ Width and Depth Expansion Capability

■ 64-pin TQFP and 64-pin STQFP

Retransmit and Synchronous Almost Full/Almost Empty flag

features are available on these devices. Depth expansion is

possible using the Cascade Input (WXI, RXI), Cascade Output

(WXO, RXO), and First Load (FL) pins. The WXO and RXO pins are

connected to the WXI and RXI pins of the next device, and the WXO

and RXO pins of the last device should be connected to the WXI and

RXI pins of the first device. The FL pin of the first device is tied to V_SS

■ Pin-compatible Density Upgrade to CY7C42X5 Family

■ Pin-compatible Density Upgrade to IDT72205/15/25/35/45

■ Pb-free Packages Available

and the FL pin of all the remaining devices should be tied to V_CC

D_0–17

Logic Block Diagram

INPUT

WCLK

WEN

FLAG

PROGRAM

WRITE

CONTROL

FLAG

LOGIC

RAM

ARRAY

8K x 18

PAE

PAF

SMODE

16K x 18

WRITE

POINTER

READ

POINTER

RESET

LOGIC

FL/RT

THREE–STATE

READ

WXI

WXO/HF

RXI

OUTPUTREGISTER

CONTROL

EXPANSION

LOGIC

Q_0–17

RXO

RCLK

REN

Note

1. CY7C4265 and CY7C4265A are functionally identical

Cypress Semiconductor Corporation

Document #: 38-06004 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 03, 2009

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与CY7C4265A-15ASI相关器件

型号	品牌	获取价格	描述	数据表
CY7C4265V	CYPRESS	获取价格	32K/64Kx18 Low Voltage Deep Sync FIFOs
CY7C4265V-10ASC	CYPRESS	获取价格	32K/64Kx18 Low Voltage Deep Sync FIFOs
CY7C4265V-15ASC	CYPRESS	获取价格	32K/64Kx18 Low Voltage Deep Sync FIFOs
CY7C4265V-15ASCT	CYPRESS	获取价格	FIFO, 16KX18, 10ns, Synchronous, CMOS, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, STQFP-
CY7C4265V-15ASI	ETC	获取价格	x18 Synchronous FIFO
CY7C4265V-15JI	CYPRESS	获取价格	FIFO, 16KX18, 10ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4265V-25ASC	CYPRESS	获取价格	32K/64Kx18 Low Voltage Deep Sync FIFOs
CY7C4265V-25JCT	CYPRESS	获取价格	FIFO, 16KX18, 15ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4271	CYPRESS	获取价格	16K/32K x 9 Deep Sync FIFOs
CY7C4271-10AC	CYPRESS	获取价格	16K/32K x 9 Deep Sync FIFOs

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