Datasheet > 存储 > FIFO> CY7C4265-15ACT

CY7C4265-15ACT

更新时间： 2024-02-11 10:48:38

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片
页数	文件大小	规格书
22页	351K
描述
FIFO, 16KX18, 10ns, Synchronous, CMOS, PQFP64, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-64

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技术参数
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CY7C4265-15ACT 技术参数

生命周期：	Obsolete	零件包装代码：	LCC
包装说明：	QCCJ,	针数：	68
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.82
最长访问时间：	10 ns	其他特性：	RETRANSMIT
周期时间：	15 ns	JESD-30 代码：	S-PQCC-J68
长度：	24.2316 mm	内存密度：	294912 bit
内存宽度：	18	功能数量：	1
端子数量：	68	字数：	16384 words
字数代码：	16000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	16KX18	输出特性：	3-STATE
可输出：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	并行/串行：	PARALLEL
认证状态：	Not Qualified	座面最大高度：	5.08 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	宽度：	24.2316 mm

CY7C4265-15ACT 数据手册

CY7C4255

CY7C4265

Signal Name

D_{0 –17}

Description

Data Inputs

I/O

Function

Data inputs for an 18-bit bus.

Data outputs for an 18-bit bus.

Enables the WCLK inpu.t

Enables the RCLK input.

Q_0–17

Data Outputs

Write Enable

Read Enable

Write Clock

WEN

REN

WCLK

The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not

Full. When LD is asserted, WCLK writes data into the programmable flag-offset

RCLK

Read Clock

The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not

Empty. When LD is asserted, RCLK reads data out of the programmable flag-off-

set register.

WXO/HF

Write Expansion

Out/Half Full Flag

Dual-Mode Pin:

Single device or width expansion – Half Full status flag.

Cascaded – Write Expansion Out signal, connected to WXI of next device.

Empty Flag

Full Flag

When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.

When FF is LOW, the FIFO is full. FF is synchronized to WCLK.

PAE

Programmable

Almost Empty

When PAE is LOW, the FIFO is almost empty based on the almost-empty offset

value programmed into the FIFO. PAE is asynchronous when V_CC/SMODE is tied

to V_CC; it is synchronized to RCLK when V_CC/SMODE is tied to V_SS

PAF

Programmable

Almost Full

When PAF is LOW, the FIFO is almost full based on the almost full offset value

programmed into the FIFO. PAF is asynchronous when V_CC/SMODE is tied to

V_CC; it is synchronized to WCLK when V_CC/SMODE is tied to V_SS

Load

When LD is LOW, D_0–17(Q_0–17) are written (read) into (from) the programma-

ble-flag-offset register.

FL/RT

First Load/

Retransmit

Dual-Mode Pin:

Cascaded – The first device in the daisy chain will have FL tied to V_SS; all other

devices will have FL tied to V_CC. In standard mode or width expansion, FL is tied

to V_SSon all devices.

Not Cascaded – Tied to V_SS. Retransmit function is also available in stand-alone

mode by strobing RT.

WXI

RXI

RXO

Write Expansion

Input

Cascaded – Connected to WXO of previous device.

Not Cascaded – Tied to V_SS

Cascaded – Connected to RXO of previous device.

Not Cascaded – Tied to V_SS

Read Expansion

Input

Read Expansion

Output

Cascaded – Connected to RXI of next device.

Reset

Resets device to empty condition. A reset is required before an initial read or write

operation after power-up.

Output Enable

When OE is LOW, the FIFO’s data outputs drive the bus to which they are con-

nected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.

V_CC/SMODE Synchronous

Almost Empty/

Dual-Mode Pin:

Asynchronous Almost Empty/Almost Full flags – tied to V_CC

Synchronous Almost Empty/Almost Full flags – tied to V_SS

(Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.)

Almost Full Flags

Document #: 38-06004 Rev. *B

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与CY7C4265-15ACT相关器件

型号	品牌	获取价格	描述	数据表
CY7C4265-15AI	CYPRESS	获取价格	FIFO, 16KX18, 10ns, Synchronous, CMOS, PQFP64, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-6
CY7C4265-15ASC	CYPRESS	获取价格	8K/16K x 18 Deep Sync FIFOs
CY7C4265-15AXC	CYPRESS	获取价格	8K/16K x 18 Deep Sync FIFOs
CY7C4265-15JC	CYPRESS	获取价格	FIFO, 16KX18, 10ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4265-15JCR	CYPRESS	获取价格	FIFO, 16KX18, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4265-15JCT	CYPRESS	获取价格	FIFO, 16KX18, 10ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4265-15JI	CYPRESS	获取价格	FIFO, 16KX18, 10ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4265-15JIR	CYPRESS	获取价格	FIFO, 16KX18, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4265-25	CYPRESS	获取价格	8K/16K x 18 Deep Sync FIFOs
CY7C4265-25AC	CYPRESS	获取价格	FIFO, 16KX18, 15ns, Synchronous, CMOS, PQFP64, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-6

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