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CY7C4235V-15ASXC PDF预览

CY7C4235V-15ASXC

更新时间： 2024-11-28 05:09:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 先进先出芯片
页数 文件大小 规格书
20页 564K
描述
64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs

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中文翻译

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CY7C4235V-15ASXC 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFP包装说明：LFQFP, QFP64,.47SQ,20
针数：64Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.71
Factory Lead Time：1 week风险等级：5.43
最长访问时间：11 ns其他特性：RETRANSMIT
最大时钟频率 (fCLK)：66.7 MHz周期时间：15 ns
JESD-30 代码：S-PQFP-G64JESD-609代码：e3
长度：10 mm内存密度：36864 bit
内存集成电路类型：OTHER FIFO内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：64字数：2048 words
字数代码：2000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：2KX18可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装等效代码：QFP64,.47SQ,20封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.006 A子类别：FIFOs
最大压摆率：0.03 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：20
宽度：10 mmBase Number Matches：1

CY7C4235V-15ASXC 数据手册

 浏览型号CY7C4235V-15ASXC的Datasheet PDF文件第2页浏览型号CY7C4235V-15ASXC的Datasheet PDF文件第3页浏览型号CY7C4235V-15ASXC的Datasheet PDF文件第4页浏览型号CY7C4235V-15ASXC的Datasheet PDF文件第5页浏览型号CY7C4235V-15ASXC的Datasheet PDF文件第6页浏览型号CY7C4235V-15ASXC的Datasheet PDF文件第7页 
CY7C4425V /4205V/4215V CY7C4225V /4235V/4245V64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs  
CY7C4225V/4205V/4215V  
CY7C4425V/4235V/4245V  
64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs  
Features  
Functional Description  
• 3.3V operation for low power consumption and easy  
integration into low-voltage systems  
The CY7C42X5V are high-speed, low-power, first-in first-out  
(FIFO) memories with clocked read and write interfaces. All  
are 18 bits wide. The CY7C42X5V can be cascaded to  
increase FIFO depth. Programmable features include Almost  
Full/Almost Empty flags. These FIFOs provide solutions for a  
wide variety of data buffering needs, including high-speed data  
acquisition, multiprocessor interfaces, and communications  
buffering.  
• High-speed, low-power, first-in first-out (FIFO)  
memories  
• 64 x 18 (CY7C4425V)  
• 256 x 18 (CY7C4205V)  
• 512 x 18 (CY7C4215V)  
• 1K x 18 (CY7C4225V)  
• 2K x 18 (CY7C4235V)  
• 4K x 18 (CY7C4245V)  
• 0.65µ CMOS  
These FIFOs have 18-bit input and output ports that are  
controlled by separate clock and enable signals. The input port  
is controlled by a Free-Running Clock (WCLK) and a Write  
Enable pin (WEN).  
When WEN is asserted, data is written into the FIFO on the  
rising edge of the WCLK signal. While WEN is held active, data  
is continually written into the FIFO on each cycle. The output  
port is controlled in a similar manner by a Free-Running Read  
Clock (RCLK) and a Read Enable pin (REN). In addition, the  
CY7C42X5V have an Output Enable pin (OE). The read and  
write clocks may be tied together for single-clock operation or  
the two clocks may be run independently for asynchronous  
read/write applications. Clock frequencies up to 66 MHz are  
achievable.  
• High-speed 67-MHz operation (15-ns read/write cycle  
times)  
• Low power  
— ICC = 30 mA  
• 5V tolerant inputs (VIH MAX = 5V)  
• Fully asynchronous and simultaneous read and write  
operation  
Retransmit and Synchronous Almost Full/Almost Empty flag  
features are available on these devices.  
• Empty, Full, HalfFull, andprogrammableAlmostEmpty  
and Almost Full status flags  
Depth expansion is possible using the Cascade Input (WXI,  
RXI), Cascade Output (WXO, RXO), and First Load (FL) pins.  
The WXO and RXO pins are connected to the WXI and RXI  
pins of the next device, and the WXO and RXO pins of the last  
device should be connected to the WXI and RXI pins of the  
first device. The FL pin of the first device is tied to VSS and the  
• TTL-compatible  
• Retransmit function  
• Output Enable (OE) pin  
• Independent read and write enable pins  
• Supports free-running 50% duty cycle clock inputs  
• Width-Expansion Capability  
FL pin of all the remaining devices should be tied to VCC  
.
The CY7C42X5V provides five status pins. These pins are  
decoded to determine one of five states: Empty, Almost Empty,  
Half Full, Almost Full, and Full (see Table 2). The Half Full flag  
shares the WXO pin. This flag is valid in the stand-alone and  
width-expansion configurations. In the depth expansion, this  
pin provides the expansion out (WXO) information that is used  
to signal the next FIFO when it will be activated.  
• Depth-Expansion Capability  
• 64-pin 14 × 14 TQFP and 64-pin 10 × 10 STQFP  
• Pb-Free packages available  
The Empty and Full flags are synchronous, i.e., they change  
state relative to either the Read Clock (RCLK) or the write  
clock (WCLK). When entering or exiting the Empty states, the  
flag is updated exclusively by the RCLK. The flag denoting Full  
states is updated exclusively by WCLK. The synchronous flag  
architecture guarantees that the flags will remain valid from  
one clock cycle to the next. As mentioned previously, the  
Almost Empty/Almost Full flags become synchronous if the  
V
CC/SMODE is tied to VSS. All configurations are fabricated  
using an advanced 0.65µ P-Well CMOS technology. Input  
ESD protection is greater than 2001V, and latch-up is  
prevented by the use of guard rings.  
Cypress Semiconductor Corporation  
Document #: 38-06029 Rev. *C  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised September 7, 2005  
1234567...20

中文翻译

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CY7C4235V-15ASXC 替代型号

型号 品牌 替代类型 描述 数据表
CY7C4235V-15ASC CYPRESS

完全替代

 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4235-35ASC CYPRESS

功能相似

 64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs
CY7C4235-10ASC CYPRESS

功能相似

 64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs

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CY7C4235V-25JCR CYPRESS

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CY7C4235V-35ASC CYPRESS

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 		64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4235V-35JCR CYPRESS

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CY7C4235V-35JCT CYPRESS

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 		FIFO, 2KX18, 20ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4241 CYPRESS

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 		64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

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