Datasheet > 存储 > FIFO> CY7C4225V-35JC

CY7C4225V-35JC

更新时间： 2024-11-28 13:07:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片
页数	文件大小	规格书
25页	411K
描述
FIFO, 1KX18, 20ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68

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技术参数
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CY7C4225V-35JC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	LCC	包装说明：	PLASTIC, LCC-68
针数：	68	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.71
风险等级：	5.82	Is Samacsys：	N
最长访问时间：	20 ns	其他特性：	RETRANSMIT
最大时钟频率 (fCLK)：	28.6 MHz	周期时间：	35 ns
JESD-30 代码：	S-PQCC-J68	JESD-609代码：	e0
长度：	24.2316 mm	内存密度：	18432 bit
内存集成电路类型：	OTHER FIFO	内存宽度：	18
功能数量：	1	端子数量：	68
字数：	1024 words	字数代码：	1000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	1KX18
输出特性：	3-STATE	可输出：	YES
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	LDCC68,1.0SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	3.3 V
认证状态：	Not Qualified	座面最大高度：	5.08 mm
最大待机电流：	0.006 A	子类别：	FIFOs
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	24.2316 mm
Base Number Matches：	1

CY7C4225V-35JC 数据手册

1CY7C4225

fax id: 5410

CY7C4425/4205/4215

CY7C4225/4235/4245

64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs

controlled by a free-running clock (WCLK) and a write enable

pin (WEN).

Features

• High-speed, low-power, first-in first-out (FIFO)

When WEN is asserted, data is written into the FIFO on the

rising edge of the WCLK signal. While WEN is held active, data

is continually written into the FIFO on each cycle. The output

port is controlled in a similar manner by a free-running read

clock (RCLK) and a read enable pin (REN). In addition, the

CY7C42X5 have an output enable pin (OE). The read and

write clocks may be tied together for single-clock operation or

the two clocks may be run independently for asynchronous

read/write applications. Clock frequencies up to 100 MHz are

achievable.

memories

• 64 x 18 (CY7C4425)

• 256 x 18 (CY7C4205)

• 512 x 18 (CY7C4215)

• 1K x 18 (CY7C4225)

• 2K x 18 (CY7C4235)

• 4K x 18 (CY7C4245)

• High-speed 100-MHz operation (10 ns read/write cycle

time)

Retransmit and Synchronous Almost Full/Almost Empty flag

features are available on these devices.

• Low power (I =45 mA)

• Fully asynchronous and simultaneous read and write

operation

• Empty, Full, Half Full, and Programmable Almost

Empty/Almost Full status flags

• TTL-compatible

• Retransmit function

• Output Enable (OE) pin

• Independent read and write enable pins

• Center power and ground for reduced noise

• Supports free-running 50% duty cycle clock inputs

• Width Expansion Capability

Depth expansion is possible using the cascade input (WXI,

RXI), cascade output (WXO, RXO), and First Load (FL) pins.

The WXO and RXO pins are connected to the WXI and RXI

pins of the next device, and the WXO and RXO pins of the last

device should be connected to the WXI and RXI pins of the

first device. The FL pin of the first device is tied to V and the

FL pin of all the remaining devices should be tied to V

The CY7C42X5 provides five status pins. These pins are de-

coded to determine one of five states: Empty, Almost Empty,

Half Full, Almost Full, and Full (see Table 2). The Half Full flag

shares the WXO pin. This flag is valid in the standalone and

width-expansion configurations. In the depth expansion, this

pin provides the expansion out (WXO) information that is used

to signal the next FIFO when it will be activated.

• Depth Expansion Capability

• Space saving 64-pin 10x10 TQFP, and 14x14 TQFP

• 68-pin PLCC

The Empty and Full flags are synchronous, i.e., they change

state relative to either the read clock (RCLK) or the write clock

(WCLK). When entering or exiting the Empty states, the flag is

updated exclusively by the RCLK. The flag denoting Full states

is updated exclusively by WCLK. The synchronous flag archi-

tecture guarantees that the flags will remain valid from one

clock cycle to the next. As mentioned previously, the Almost

Empty/Almost Full flags become synchronous if the

Functional Description

The CY7C42X5 are high-speed, low-power, first-in first-out

(FIFO) memories with clocked read and write interfaces. All

are 18 bits wide and are pin/functionally compatible to

IDT722x5. The CY7C42X5 can be cascaded to increase FIFO

depth. Programmable features include Almost Full/Almost

Empty flags. These FIFOs provide solutions for a wide variety

of data buffering needs, including high-speed data acquisition,

multiprocessor interfaces, and communications buffering.

/SMODE is tied to V . All configurations are fabricated

using an advanced 0.65µ N-Well CMOS technology. Input

ESD protection is greater than 2001V, and latch-up is prevent-

ed by the use of guard rings.

These FIFOs have 18-bit input and output ports that are con-

trolled by separate clock and enable signals. The input port is

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

April 1995 - Revised August 18, 1997

12 3 4 5 6 7...25

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与CY7C4225V-35JC相关器件

型号	品牌	获取价格	描述	数据表
CY7C4225V-35JCT	CYPRESS	获取价格	FIFO, 1KX18, 20ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4231	CYPRESS	获取价格	64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
CY7C4231-10AC	CYPRESS	获取价格	64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
CY7C4231-10ACT	CYPRESS	获取价格	暂无描述
CY7C4231-10AI	CYPRESS	获取价格	FIFO, 2KX9, 8ns, Synchronous, CMOS, PQFP32, 7 X 7 MM, 1 MM HEIGHT, PLASTIC, TQFP-32
CY7C4231-10JC	CYPRESS	获取价格	64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
CY7C4231-10JCR	CYPRESS	获取价格	FIFO, 2KX9, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C4231-10JCT	CYPRESS	获取价格	FIFO, 2KX9, 8ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C4231-10JI	CYPRESS	获取价格	FIFO, 2KX9, 8ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C4231-15AC	CYPRESS	获取价格	64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

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