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CY7C4231-10AI

更新时间： 2024-02-09 20:38:34
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
21页 329K
描述
FIFO, 2KX9, 8ns, Synchronous, CMOS, PQFP32, 7 X 7 MM, 1 MM HEIGHT, PLASTIC, TQFP-32

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CY7C4231-10AI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：7 X 7 MM, 1 MM HEIGHT, PLASTIC, TQFP-32
针数：32Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.32.00.71
风险等级：5.82最长访问时间：8 ns
最大时钟频率 (fCLK)：100 MHz周期时间：10 ns
JESD-30 代码：S-PQFP-G32JESD-609代码：e0
长度：7 mm内存密度：18432 bit
内存集成电路类型：OTHER FIFO内存宽度：9
功能数量：1端子数量：32
字数：2048 words字数代码：2000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：2KX9
输出特性：3-STATE可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：TQFP
封装等效代码：TQFP32,.35SQ,32封装形状：SQUARE
封装形式：FLATPACK, THIN PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：240电源：5 V
认证状态：Not Qualified座面最大高度：1.2 mm
最大待机电流：0.04 A子类别：FIFOs
最大压摆率：0.17 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.8 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：7 mmBase Number Matches：1

CY7C4231-10AI 数据手册

 浏览型号CY7C4231-10AI的Datasheet PDF文件第2页浏览型号CY7C4231-10AI的Datasheet PDF文件第3页浏览型号CY7C4231-10AI的Datasheet PDF文件第4页浏览型号CY7C4231-10AI的Datasheet PDF文件第5页浏览型号CY7C4231-10AI的Datasheet PDF文件第6页浏览型号CY7C4231-10AI的Datasheet PDF文件第7页 
241/42  
CY7C4421/4201/4211/4221  
CY7C4231/4241/4251  
64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs  
Features  
Functional Description  
• High-speed, low-power, first-in, first-out (FIFO)  
memories  
THe CY7C42X1 are high-speed, low-power, first-in first-out  
(FIFO) memories with clocked read and write interfaces. All  
are 9 bits wide. The CY7C42X1 are pin-compatible to  
IDT722X1. Programmable features include Almost Full/Almost  
Empty flags. These FIFOs provide solutions for a wide variety  
of data buffering needs, including high-speed data acquisition,  
multiprocessor interfaces, and communications buffering.  
• 64 x 9 (CY7C4421)  
• 256 x 9 (CY7C4201)  
• 512 x 9 (CY7C4211)  
• 1K x 9 (CY7C4221)  
• 2K x 9 (CY7C4231)  
• 4K x 9 (CY7C4241)  
• 8K x 9 (CY7C4251)  
These FIFOs have 9-bit input and output ports that are con-  
trolled by separate clock and enable signals. The input port is  
controlled by a free-running clock (WCLK) and two write-en-  
able pins (WEN1, WEN2/LD).  
• High-speed 100-MHz operation (10 ns read/write cycle  
time)  
When WEN1 is LOW and WEN2/LD is HIGH, data is written  
into the FIFO on the rising edge of the WCLK signal. While  
WEN1, WEN2/LD is held active, data is continually written into  
the FIFO on each WCLK cycle. The output port is controlled in  
a similar manner by a free-running read clock (RCLK) and two  
read-enable pins (REN1, REN2). In addition, the CY7C42X1  
has an output enable pin (OE). The read (RCLK) and write  
(WCLK) clocks may be tied together for single-clock operation  
or the two clocks may be run independently for asynchronous  
read/write applications. Clock frequencies up to 100 MHz are  
achievable.  
• Low power (I = 35 mA)  
CC  
• Fully asynchronous and simultaneous read and write  
operation  
• Empty, Full, and Programmable Almost Empty and  
Almost Full status flags  
• TTL-compatible  
• Expandable in width  
• Output Enable (OE) pin  
• Independant read and write enable pins  
• Center power and ground pins for reduced noise  
• Width Expansion Capability  
• Space saving 7mm x 7mm 32-pin TQFP  
• 32-pin PLCC  
Depth expansion is possible using one enable input for system  
control, while the other enable is controlled by expansion logic  
to direct the flow of data.  
• PincompatibleandfunctionallyequivalenttoIDT72421,  
72201, 72211, 72221, 72231, 72241  
Logic Block Diagram  
Pin Configuration  
D
0- 8  
PLCC  
Top View  
INPUT  
REGISTER  
4
3
2
1 323130  
29  
28  
D
D
PAF  
PAE  
GND  
REN1  
RCLK  
REN2  
OE  
1
RS  
WEN1  
5
6
7
8
9
0
27 WCLK  
26  
25  
24  
23  
22  
21  
WCLKWEN1 WEN2/LD  
WEN2/LD  
V
CC  
FLAG  
PROGRAM  
REGISTER  
Q
10  
11  
12  
13  
8
7
Q
Q
Q
6
5
WRITE  
CONTROL  
14151617181920  
EF  
42X1–2  
PAE  
PAF  
FF  
FLAG  
LOGIC  
Dual Port  
RAM Array  
64x 9  
TQFP  
Top View  
WRITE  
POINTER  
READ  
POINTER  
8k x 9  
32 31 30 29 28 27 26 25  
1
2
3
4
5
6
7
8
24  
23  
WEN1  
D
D
1
0
RESET  
LOGIC  
RS  
WCLK  
WEN2/LD  
22  
21  
20  
19  
PAF  
PAE  
GND  
REN1  
V
CC  
THREE-STATE  
OUTPUTREGISTER  
Q
Q
8
7
READ  
CONTROL  
Q
Q
6
5
RCLK  
REN2  
18  
17  
OE  
9 10 11 12 13 14 15 16  
Q
0- 8  
RCLK REN1 REN2  
42X1–3  
42X1–1  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
March 1995 - Revised September 30, 1997  
1234567...21

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