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CY7C4231-15JXC PDF预览

CY7C4231-15JXC

更新时间： 2024-02-26 19:39:37
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 先进先出芯片
页数 文件大小 规格书
19页 547K
描述
64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

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中文翻译

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CY7C4231-15JXC 技术参数

生命周期：Active零件包装代码：QFJ
包装说明：QCCJ,针数：32
Reach Compliance Code：unknown风险等级：5.75
最长访问时间：10 ns周期时间：15 ns
JESD-30 代码：R-PQCC-J32JESD-609代码：e0
长度：13.97 mm内存密度：18432 bit
内存宽度：9功能数量：1
端子数量：32字数：2048 words
字数代码：2000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：2KX9可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装形状：RECTANGULAR封装形式：CHIP CARRIER
并行/串行：PARALLEL认证状态：COMMERCIAL
座面最大高度：3.55 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：TIN LEAD
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD宽度：11.43 mm
Base Number Matches：1

CY7C4231-15JXC 数据手册

 浏览型号CY7C4231-15JXC的Datasheet PDF文件第2页浏览型号CY7C4231-15JXC的Datasheet PDF文件第3页浏览型号CY7C4231-15JXC的Datasheet PDF文件第4页浏览型号CY7C4231-15JXC的Datasheet PDF文件第5页浏览型号CY7C4231-15JXC的Datasheet PDF文件第6页浏览型号CY7C4231-15JXC的Datasheet PDF文件第7页 
CY7C4421/4201/4211/4221 CY7C4231/4241/425164/256/512/1K/2K/4K/8K  
x 9 Synchronous FIFOs  
CY7C4421/4201/4211/4221  
CY7C4231/4241/4251  
64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs  
• Pb-Free Packages Available  
Features  
Functional Description  
• High-speed, low-power, First-In, First-Out (FIFO)  
memories  
The CY7C42X1 are high-speed, low-power FIFO memories  
with clocked Read and Write interfaces. All are 9 bits wide. The  
CY7C42X1 are pin-compatible to IDT722X1. Programmable  
features include Almost Full/Almost Empty flags. These FIFOs  
provide solutions for a wide variety of data buffering needs,  
including high-speed data acquisition, multiprocessor inter-  
faces, and communications buffering.  
— 64 × 9 (CY7C4421)  
— 256 × 9 (CY7C4201)  
— 512 × 9 (CY7C4211)  
— 1K × 9 (CY7C4221)  
— 2K × 9 (CY7C4231)  
— 4K × 9 (CY7C4241)  
— 8K × 9 (CY7C4251)  
These FIFOs have 9-bit input and output ports that are  
controlled by separate clock and enable signals. The input port  
is controlled by a free-running clock (WCLK) and two  
Write-enable pins (WEN1, WEN2/LD).  
• High-speed 100-MHz operation (10 ns Read/Write cycle  
time)  
• Low power (ICC = 35 mA)  
When WEN1 is LOW and WEN2/LD is HIGH, data is written  
into the FIFO on the rising edge of the WCLK signal. While  
WEN1, WEN2/LD is held active, data is continually written into  
the FIFO on each WCLK cycle. The output port is controlled in  
a similar manner by a free-running Read clock (RCLK) and two  
Read-enable pins (REN1, REN2). In addition, the CY7C42X1  
has an output enable pin (OE). The Read (RCLK) and Write  
(WCLK) clocks may be tied together for single-clock operation  
or the two clocks may be run independently for asynchronous  
Read/Write applications. Clock frequencies up to 100 MHz are  
achievable.  
• Fully asynchronous and simultaneous Read and Write  
operation  
• Empty, Full, and Programmable Almost Empty and  
Almost Full status flags  
• TTL-compatible  
• Expandable in width  
• Output Enable (OE) pin  
• Independent Read and Write enable pins  
• Center power and ground pins for reduced noise  
• Width-expansion capability  
Depth expansion is possible using one enable input for system  
control, while the other enable is controlled by expansion logic  
to direct the flow of data.  
• Space saving 7 mm × 7 mm 32-pin TQFP  
• Pin-compatible and functionally equivalent to  
IDT72421, 72201, 72211, 72221, 72231, and 72241  
D
0- 8  
Pin Configurations  
Logic Block Diagram  
PLCC  
Top View  
INPUT  
REGISTER  
4
3
2
1 323130  
29  
28  
D
D
PAF  
PAE  
GND  
REN1  
RCLK  
REN2  
OE  
RS  
WEN1  
1
0
5
6
7
8
9
WCLKWEN1 WEN2/LD  
27 WCLK  
26  
25  
24  
23  
22  
21  
WEN2/LD  
FLAG  
PROGRAM  
REGISTER  
V
CC  
Q
Q
Q
Q
10  
11  
12  
13  
8
7
6
5
Write  
CONTROL  
EF  
14151617181920  
PAE  
PAF  
FF  
FLAG  
LOGIC  
Dual Port  
RAM Array  
64 x 9  
TQFP  
Top View  
Write  
POINTER  
Read  
POINTER  
32 31 30 29 28 27 26 25  
8k x 9  
1
2
3
4
5
6
7
8
24  
WEN1  
D
D
1
0
23  
WCLK  
WEN2/LD  
22  
21  
20  
19  
PAF  
PAE  
RESET  
LOGIC  
RS  
V
Q
CC  
8
GND  
Q
7
REN1  
RCLK  
REN2  
Q
Q
THREE-STATE  
OUTPUT REGISTER  
6
5
18  
17  
Read  
CONTROL  
9
10 11 12 13 14 15 16  
OE  
Q
0- 8  
RCLK REN1 REN2  
Cypress Semiconductor Corporation  
Document #: 38-06016 Rev. *C  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised August 2, 2005  
1234567...19

中文翻译

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与CY7C4231-15JXC相关器件

型号 品牌 获取价格 描述 数据表
CY7C4231-25AC CYPRESS

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 		64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
CY7C4231-25JC CYPRESS

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 		64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
CY7C4231-25JCR CYPRESS

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 		FIFO, 2KX9, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C4231-25JCT CYPRESS

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 		FIFO, 2KX9, 15ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C4231-25JI CYPRESS

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 		FIFO, 2KX9, 15ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C4231-25JIR CYPRESS

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 		FIFO, 2KX9, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C4231-35AC CYPRESS

获取价格

 		FIFO, 2KX9, 20ns, Synchronous, CMOS, PQFP32, 7 X 7 MM, 1 MM HEIGHT, PLASTIC, TQFP-32
CY7C4231-35JCR CYPRESS

获取价格

 		FIFO, 2KX9, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C4231-35JCT CYPRESS

获取价格

 		FIFO, 2KX9, 20ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C4231-35JI CYPRESS

获取价格

 		FIFO, 2KX9, 20ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32

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