CY7C4421/4201/4211/4221 CY7C4231/4241/425164/256/512/1K/2K/4K/8K
x 9 Synchronous FIFOs
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
• Pb-Free Packages Available
Features
Functional Description
• High-speed, low-power, First-In, First-Out (FIFO)
memories
The CY7C42X1 are high-speed, low-power FIFO memories
with clocked Read and Write interfaces. All are 9 bits wide. The
CY7C42X1 are pin-compatible to IDT722X1. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs,
including high-speed data acquisition, multiprocessor inter-
faces, and communications buffering.
— 64 × 9 (CY7C4421)
— 256 × 9 (CY7C4201)
— 512 × 9 (CY7C4211)
— 1K × 9 (CY7C4221)
— 2K × 9 (CY7C4231)
— 4K × 9 (CY7C4241)
— 8K × 9 (CY7C4251)
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
Write-enable pins (WEN1, WEN2/LD).
• High-speed 100-MHz operation (10 ns Read/Write cycle
time)
• Low power (ICC = 35 mA)
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a free-running Read clock (RCLK) and two
Read-enable pins (REN1, REN2). In addition, the CY7C42X1
has an output enable pin (OE). The Read (RCLK) and Write
(WCLK) clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
Read/Write applications. Clock frequencies up to 100 MHz are
achievable.
• Fully asynchronous and simultaneous Read and Write
operation
• Empty, Full, and Programmable Almost Empty and
Almost Full status flags
• TTL-compatible
• Expandable in width
• Output Enable (OE) pin
• Independent Read and Write enable pins
• Center power and ground pins for reduced noise
• Width-expansion capability
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic
to direct the flow of data.
• Space saving 7 mm × 7 mm 32-pin TQFP
• Pin-compatible and functionally equivalent to
IDT72421, 72201, 72211, 72221, 72231, and 72241
D
0- 8
Pin Configurations
Logic Block Diagram
PLCC
Top View
INPUT
REGISTER
4
3
2
1 323130
29
28
D
D
PAF
PAE
GND
REN1
RCLK
REN2
OE
RS
WEN1
1
0
5
6
7
8
9
WCLKWEN1 WEN2/LD
27 WCLK
26
25
24
23
22
21
WEN2/LD
FLAG
PROGRAM
REGISTER
V
CC
Q
Q
Q
Q
10
11
12
13
8
7
6
5
Write
CONTROL
EF
14151617181920
PAE
PAF
FF
FLAG
LOGIC
Dual Port
RAM Array
64 x 9
TQFP
Top View
Write
POINTER
Read
POINTER
32 31 30 29 28 27 26 25
8k x 9
1
2
3
4
5
6
7
8
24
WEN1
D
D
1
0
23
WCLK
WEN2/LD
22
21
20
19
PAF
PAE
RESET
LOGIC
RS
V
Q
CC
8
GND
Q
7
REN1
RCLK
REN2
Q
Q
THREE-STATE
OUTPUT REGISTER
6
5
18
17
Read
CONTROL
9
10 11 12 13 14 15 16
OE
Q
0- 8
RCLK REN1 REN2
Cypress Semiconductor Corporation
Document #: 38-06016 Rev. *C
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised August 2, 2005