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CY7C4225-15AXCT

更新时间： 2024-02-01 03:27:21
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
22页 436K
描述
FIFO, 1KX18, 10ns, Synchronous, CMOS, PQFP64, 14 X 14 MM, LEAD FREE, PLASTIC, TQFP-64

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CY7C4225-15AXCT 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP, QFP64,.63SQ,32
针数：64Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.71
风险等级：5.49最长访问时间：10 ns
其他特性：RETRANSMIT最大时钟频率 (fCLK)：66.7 MHz
周期时间：15 nsJESD-30 代码：S-PQFP-G64
JESD-609代码：e4长度：14 mm
内存密度：18432 bit内存集成电路类型：OTHER FIFO
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：64
字数：1024 words字数代码：1000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：1KX18
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP64,.63SQ,32
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL电源：5 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.01 A子类别：FIFOs
最大压摆率：0.045 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.8 mm
端子位置：QUAD宽度：14 mm
Base Number Matches：1

CY7C4225-15AXCT 数据手册

 浏览型号CY7C4225-15AXCT的Datasheet PDF文件第2页浏览型号CY7C4225-15AXCT的Datasheet PDF文件第3页浏览型号CY7C4225-15AXCT的Datasheet PDF文件第4页浏览型号CY7C4225-15AXCT的Datasheet PDF文件第6页浏览型号CY7C4225-15AXCT的Datasheet PDF文件第7页浏览型号CY7C4225-15AXCT的Datasheet PDF文件第8页 
CY7C4425/4205/4215  
CY7C4225/4235/4245  
that the FIFO is either Almost Full or Almost Empty. See Table 2  
for a description of programmable flags.  
Flag Operation  
The CY7C42X5 devices provide five flag pins to indicate the  
condition of the FIFO contents. Empty and Full are synchronous.  
When the SMODE pin is tied LOW, the PAF flag signal transition  
is caused by the rising edge of the write clock and the PAE flag  
transition is caused by the rising edge of the read clock.  
PAE and PAF are synchronous if VCC/SMODE is tied to VSS  
.
Full Flag  
Retransmit  
The Full Flag (FF) will go LOW when device is Full. Write opera-  
tions are inhibited whenever FF is LOW regardless of the state  
of WEN. FF is synchronized to WCLK, i.e., it is exclusively  
updated by each rising edge of WCLK.  
The retransmit feature is beneficial when transferring packets of  
data. It enables the receipt of data to be acknowledged by the  
receiver and retransmitted if necessary.  
The Retransmit (RT) input is active in the standalone and width  
expansion modes. The retransmit feature is intended for use  
when a number of writes equal to or less than the depth of the  
FIFO have occurred since the last RS cycle. A HIGH pulse on  
RT resets the internal read pointer to the first physical location of  
the FIFO. WCLK and RCLK may be free running but must be  
disabled during and tRTR after the retransmit pulse. With every  
valid read cycle after retransmit, previously accessed data is  
read and the read pointer is incremented until it is equal to the  
write pointer. Flags are governed by the relative locations of the  
read and write pointers and are updated during a retransmit  
cycle. Data written to the FIFO after activation of RT are trans-  
mitted also.  
Empty Flag  
The Empty Flag (EF) will go LOW when the device is empty.  
Read operations are inhibited whenever EF is LOW, regardless  
of the state of REN. EF is synchronized to RCLK, i.e., it is exclu-  
sively updated by each rising edge of RCLK.  
Programmable Almost Empty/Almost Full Flag  
The CY7C42X5 features programmable Almost Empty and  
Almost Full Flags. Each flag can be programmed (described in  
the Programming section) a specific distance from the corre-  
sponding boundary flags (Empty or Full). When the FIFO  
contains the number of words or fewer for which the flags have  
been programmed, the PAF or PAE will be asserted, signifying  
The full depth of the FIFO can be repeatedly retransmitted.  
Table 2. Flag Truth Table  
Number of Words in FIFO  
CY7C4425 - 64 x 18  
CY7C4205 - 256 x 18  
CY7C4215 - 512 x 18  
FF  
H
H
H
H
H
L
PAF  
H
HF  
H
H
H
L
PAE  
L
EF  
L
0
0
0
1 to n[2]  
1 to n[2]  
1 to n[2]  
H
L
H
H
H
H
H
(n + 1) to 32  
33 to (64 − (m + 1))  
(64 − m)[] to 63  
64  
(n + 1) to 128  
129 to (256 − (m + 1))  
(256 − m)[] to 255  
256  
(n + 1) to 256  
257 to (512 − (m + 1))  
(512 − m)[] to 511  
512  
H
H
H
H
L
L
H
L
L
H
Number of Words in FIFO  
CY7C4235 - 2K x 18  
0
CY7C4225 - 1K x 18  
0
1 to n[2]  
CY7C4245 - 4K x 18  
0
1 to n[2]  
FF  
H
H
H
H
H
L
PAF  
H
HF  
H
H
H
L
PAE  
L
EF  
L
1 to n[2]  
H
L
H
H
H
H
H
(n + 1) to 512  
513 to (1024 − (m + 1))  
(1024 − m)[3] to 1023  
1024  
(n + 1) to 1024  
1025 to (2048 − (m + 1))  
(2048 − m)[3] to 2047  
2048  
(n + 1) to 2048  
2049 to (4096 − (m + 1))  
(4096 − m)[3] to 4095  
4096  
H
H
H
H
L
L
H
L
L
H
Note  
2. n = Empty Offset (Default Values: CY7C4425 n = 7, CY7C4205 n = 31, CY7C4215 n = 63, CY7C4225/CY7C4235/CY7C4245 n = 127).  
3. m = Full Offset (Default Values: CY7C4425 n = 7, CY7C4205 n = 31, CY7C4215 n = 63, CY7C4225/CY7C4235/CY7C4245 n = 127).  
Document Number: 001-45652 Rev. *A  
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CY7C4225-15AXCT 替代型号

型号 品牌 替代类型 描述 数据表
CY7C4225-15ASXC CYPRESS

完全替代

 256/512/1K/4K x 18 Synchronous FIFOs
CY7C4225-10AXI CYPRESS

类似代替

 256/512/1K/4K x 18 Synchronous FIFOs

与CY7C4225-15AXCT相关器件

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CY7C4225-15JC CYPRESS

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 		64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4225-15JCT CYPRESS

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 		FIFO, 1KX18, 10ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4225-15JI CYPRESS

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 		64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4225-15JIR CYPRESS

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 		FIFO, 1KX18, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4225-15JIT CYPRESS

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 		FIFO, 1KX18, 10ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4225-25AC CYPRESS

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 		64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4225-25AI CYPRESS

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 		64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4225-25ASC CYPRESS

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 		64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4225-25ASI CYPRESS

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 		64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4225-25JC CYPRESS

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 		64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs

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