Datasheet > CY7C4225-15AXCT

CY7C4225-15AXCT

更新时间： 2024-01-11 19:31:06

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟先进先出芯片内存集成电路
页数	文件大小	规格书
22页	436K
描述
FIFO, 1KX18, 10ns, Synchronous, CMOS, PQFP64, 14 X 14 MM, LEAD FREE, PLASTIC, TQFP-64

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CY7C4225-15AXCT 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	LQFP, QFP64,.63SQ,32
针数：	64	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.32.00.71
风险等级：	5.49	最长访问时间：	10 ns
其他特性：	RETRANSMIT	最大时钟频率 (fCLK)：	66.7 MHz
周期时间：	15 ns	JESD-30 代码：	S-PQFP-G64
JESD-609代码：	e4	长度：	14 mm
内存密度：	18432 bit	内存集成电路类型：	OTHER FIFO
内存宽度：	18	湿度敏感等级：	3
功能数量：	1	端子数量：	64
字数：	1024 words	字数代码：	1000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	1KX18
可输出：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装等效代码：	QFP64,.63SQ,32
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大待机电流：	0.01 A	子类别：	FIFOs
最大压摆率：	0.045 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

CY7C4225-15AXCT 数据手册

CY7C4425/4205/4215

CY7C4225/4235/4245

Pin Definitions (continued)

Signal Name

Description

Function

RXO

Read Expansion

Output

Cascaded – Connected to RXI of next device.

Reset

Resets device to empty condition. A reset is required before an initial read or write

operation after power-up.

Output Enable

When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected.

If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.

V_CC/SMODE Synchronous

Almost Empty/

Dual-Mode Pin. Asynchronous Almost Empty/Almost Full flags – tied to V_CC.

Synchronous Almost Empty/Almost Full flags – tied to V_SS. (Almost Empty synchro-

nized to RCLK, Almost Full synchronized to WCLK.)

Almost Full Flags

Architecture

Programming

The CY7C42X5 consists of an array of 64 to 4K words of 18 bits

each (implemented by a dual-port array of SRAM cells), a read

pointer, a write pointer, control signals (RCLK, WCLK, REN,

WEN, RS), and flags (EF, PAE, HF, PAF, FF). The CY7C42X5

also includes the control signals WXI, RXI, WXO, RXO for depth

expansion.

The CY7C42X5 devices contain two 12-bit offset registers. Data

present on D_0–11during a program write will determine the

distance from Empty (Full) that the Almost Empty (Almost Full)

flags become active. If the user elects not to program the FIFO’s

flags, the default offset values are used (see Table 2). When the

Load LD pin is set LOW and WEN is set LOW, data on the inputs

D_0–11is written into the Empty offset register on the first

LOW-to-HIGH transition of the write clock (WCLK). When the LD

pin and WEN are held LOW then data is written into the Full offset

Clock (WCLK). The third transition of the Write Clock (WCLK)

again writes to the Empty offset register (see Table 1). Writing all

offset registers does not have to occur at one time. One or two

offset registers can be written and then, by bringing the LD pin

HIGH, the FIFO is returned to normal read/write operation. When

the LD pin is set LOW, and WEN is LOW, the next offset register

in sequence is written.

Resetting the FIFO

Upon power-up, the FIFO must be reset with a Reset (RS) cycle.

This causes the FIFO to enter the Empty condition signified by

EF being LOW. All data outputs go LOW after the falling edge of

RS only if OE is asserted. In order for the FIFO to reset to its

default state, a falling edge must occur on RS and the user must

not read or write while RS is LOW.

FIFO Operation

The contents of the offset registers can be read on the output

lines when the LD pin is set LOW and REN is set LOW; then,

data can be read on the LOW-to-HIGH transition of the Read

Clock (RCLK).

When the WEN signal is active (LOW), data present on the D_0-17

pins is written into the FIFO on each rising edge of the WCLK

signal. Similarly, when the REN signal is active LOW, data in the

FIFO memory will be presented on the Q₀₋₁₇outputs. New data

will be presented on each rising edge of RCLK while REN is

active LOW and OE is LOW. REN must set up t_ENSbefore RCLK

for it to be a valid read function. WEN must occur t_ENSbefore

WCLK for it to be a valid write function.

Table 1. Write Offset Register

LD WEN WCLK^[1]

Selection

Writing to offset registers:

Empty Offset

An Output Enable (OE) pin is provided to three-state the Q_0–17

outputs when OE is deasserted. When OE is enabled (LOW),

data in the output register will be available to the Q₀₋₁₇outputs

after t_OE. If devices are cascaded, the OE function will only

output data on the FIFO that is read enabled.

Full Offset

No Operation

Write Into FIFO

No Operation

The FIFO contains overflow circuitry to disallow additional writes

when the FIFO is full, and underflow circuitry to disallow

additional reads when the FIFO is empty. An empty FIFO

maintains the data of the last valid read on its Q₀₋₁₇outputs even

after additional reads occur.

Note:

1. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK.

Document Number: 001-45652 Rev. *A

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CY7C4225-15AXCT 替代型号

型号	品牌	替代类型	描述	数据表
CY7C4225-15ASXC	CYPRESS	完全替代	256/512/1K/4K x 18 Synchronous FIFOs
CY7C4225-10AXI	CYPRESS	类似代替	256/512/1K/4K x 18 Synchronous FIFOs

与CY7C4225-15AXCT相关器件

型号	品牌	获取价格	描述	数据表
CY7C4225-15JC	CYPRESS	获取价格	64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4225-15JCT	CYPRESS	获取价格	FIFO, 1KX18, 10ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4225-15JI	CYPRESS	获取价格	64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4225-15JIR	CYPRESS	获取价格	FIFO, 1KX18, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4225-15JIT	CYPRESS	获取价格	FIFO, 1KX18, 10ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4225-25AC	CYPRESS	获取价格	64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4225-25AI	CYPRESS	获取价格	64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4225-25ASC	CYPRESS	获取价格	64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4225-25ASI	CYPRESS	获取价格	64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4225-25JC	CYPRESS	获取价格	64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs

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