Datasheet > CY7C4225V-15ASCT

CY7C4225V-15ASCT

更新时间： 2024-11-28 19:43:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片
页数	文件大小	规格书
20页	567K
描述
FIFO, 1KX18, 11ns, Synchronous, CMOS, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, STQFP-64

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CY7C4225V-15ASCT 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	LFQFP,
针数：	64	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.32.00.71
风险等级：	5.67	最长访问时间：	11 ns
其他特性：	RETRANSMIT	周期时间：	15 ns
JESD-30 代码：	S-PQFP-G64	JESD-609代码：	e0
长度：	10 mm	内存密度：	18432 bit
内存宽度：	18	功能数量：	1
端子数量：	64	字数：	1024 words
字数代码：	1000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	1KX18	输出特性：	3-STATE
可输出：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	240	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN LEAD
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	10 mm	Base Number Matches：	1

CY7C4225V-15ASCT 数据手册

CY7C4425V /4205V/4215V CY7C4225V /4235V/4245V64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs

CY7C4225V/4205V/4215V

CY7C4425V/4235V/4245V

64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs

Features

Functional Description

• 3.3V operation for low power consumption and easy

integration into low-voltage systems

The CY7C42X5V are high-speed, low-power, first-in first-out

(FIFO) memories with clocked read and write interfaces. All

are 18 bits wide. The CY7C42X5V can be cascaded to

increase FIFO depth. Programmable features include Almost

Full/Almost Empty flags. These FIFOs provide solutions for a

wide variety of data buffering needs, including high-speed data

acquisition, multiprocessor interfaces, and communications

buffering.

• High-speed, low-power, first-in first-out (FIFO)

memories

• 64 x 18 (CY7C4425V)

• 256 x 18 (CY7C4205V)

• 512 x 18 (CY7C4215V)

• 1K x 18 (CY7C4225V)

• 2K x 18 (CY7C4235V)

• 4K x 18 (CY7C4245V)

• 0.65µ CMOS

These FIFOs have 18-bit input and output ports that are

controlled by separate clock and enable signals. The input port

is controlled by a Free-Running Clock (WCLK) and a Write

Enable pin (WEN).

When WEN is asserted, data is written into the FIFO on the

rising edge of the WCLK signal. While WEN is held active, data

is continually written into the FIFO on each cycle. The output

port is controlled in a similar manner by a Free-Running Read

Clock (RCLK) and a Read Enable pin (REN). In addition, the

CY7C42X5V have an Output Enable pin (OE). The read and

write clocks may be tied together for single-clock operation or

the two clocks may be run independently for asynchronous

read/write applications. Clock frequencies up to 66 MHz are

achievable.

• High-speed 67-MHz operation (15-ns read/write cycle

times)

• Low power

— I_CC= 30 mA

• 5V tolerant inputs (V_{IH MAX}= 5V)

• Fully asynchronous and simultaneous read and write

operation

Retransmit and Synchronous Almost Full/Almost Empty flag

features are available on these devices.

• Empty, Full, HalfFull, andprogrammableAlmostEmpty

and Almost Full status flags

Depth expansion is possible using the Cascade Input (WXI,

RXI), Cascade Output (WXO, RXO), and First Load (FL) pins.

The WXO and RXO pins are connected to the WXI and RXI

pins of the next device, and the WXO and RXO pins of the last

device should be connected to the WXI and RXI pins of the

first device. The FL pin of the first device is tied to V_SSand the

• TTL-compatible

• Retransmit function

• Output Enable (OE) pin

• Independent read and write enable pins

• Supports free-running 50% duty cycle clock inputs

• Width-Expansion Capability

FL pin of all the remaining devices should be tied to V_CC

The CY7C42X5V provides five status pins. These pins are

decoded to determine one of five states: Empty, Almost Empty,

Half Full, Almost Full, and Full (see Table 2). The Half Full flag

shares the WXO pin. This flag is valid in the stand-alone and

width-expansion configurations. In the depth expansion, this

pin provides the expansion out (WXO) information that is used

to signal the next FIFO when it will be activated.

• Depth-Expansion Capability

• 64-pin 14 × 14 TQFP and 64-pin 10 × 10 STQFP

• Pb-Free packages available

The Empty and Full flags are synchronous, i.e., they change

state relative to either the Read Clock (RCLK) or the write

clock (WCLK). When entering or exiting the Empty states, the

flag is updated exclusively by the RCLK. The flag denoting Full

states is updated exclusively by WCLK. The synchronous flag

architecture guarantees that the flags will remain valid from

one clock cycle to the next. As mentioned previously, the

Almost Empty/Almost Full flags become synchronous if the

_CC/SMODE is tied to V_SS. All configurations are fabricated

using an advanced 0.65µ P-Well CMOS technology. Input

ESD protection is greater than 2001V, and latch-up is

prevented by the use of guard rings.

Cypress Semiconductor Corporation

Document #: 38-06029 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 7, 2005

12 3 4 5 6 7...20

中文翻译

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与CY7C4225V-15ASCT相关器件

型号	品牌	获取价格	描述	数据表
CY7C4225V-15ASXC	CYPRESS	获取价格	64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4225V-15ASXC	ROCHESTER	获取价格	1KX18 OTHER FIFO, 11ns, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, STQFP-64
CY7C4225V-15JCR	CYPRESS	获取价格	暂无描述
CY7C4225V-15JCT	CYPRESS	获取价格	FIFO, 1KX18, 11ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4225V-25ASC	CYPRESS	获取价格	64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4225V-25ASCT	CYPRESS	获取价格	暂无描述
CY7C4225V-25JC	CYPRESS	获取价格	FIFO, 1KX18, 15ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4225V-25JCR	CYPRESS	获取价格	FIFO, 1KX18, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4225V-25JCT	CYPRESS	获取价格	FIFO, 1KX18, 15ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4225V-35ASC	CYPRESS	获取价格	64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs

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