CY7C4211V-15AI

更新时间： 2024-11-18 02:53:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片
页数	文件大小	规格书
18页	522K
描述
Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C4211V-15AI 数据手册

CY7C4421V/4201V/4211V/4221VCY7C4231V/4241V/4251VLow-Voltage 64/256/512/1K/2K/4K/8K

x 9 Synchronous FIFOs

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

• Space saving 32-pin 7 mm × 7 mm TQFP

Featuresb

• 32-pin PLCC

• High-speed, low-power, first-in, first-out (FIFO)

memories

• Available in Pb-Free Packages

• 64 x 9 (CY7C4421V)

• 256 x 9 (CY7C4201V)

• 512 x 9 (CY7C4211V)

• 1K x 9 (CY7C4221V)

• 2K x 9 (CY7C4231V)

• 4K x 9 (CY7C4241V)

• 8K x 9 (CY7C4251V)

Functional Description

The CY7C42X1V are high-speed, low-power, FIFO memories

with clocked read and write interfaces. All are nine bits wide.

Programmable features include Almost Full/Almost Empty

flags. These FIFOs provide solutions for a wide variety of data

buffering needs, including high-speed data acquisition, multi-

processor interfaces, and communications buffering.

These FIFOs have 9-bit input and output ports that are

controlled by separate clock and enable signals. The input port

is controlled by a Free-Running Clock (WCLK) and two Write

Enable pins (WEN1, WEN2/LD).

• High-speed 66-MHz operation (15-ns read/write cycle

time)

• Low power (I_CC= 20 mA)

When WEN1 is LOW and WEN2/LD is HIGH, data is written

into the FIFO on the rising edge of the WCLK signal. While

WEN1, WEN2/LD is held active, data is continually written into

the FIFO on each WCLK cycle. The output port is controlled in

a similar manner by a Free-Running Read Clock (RCLK) and

two Read Enable Pins (REN1, REN2). In addition, the

CY7C42X1V has an Output Enable Pin (OE). The Read

(RCLK) and Write (WCLK) clocks may be tied together for

single-clock operation or the two clocks may be run indepen-

dently for asynchronous read/write applications. Clock

frequencies up to 66 MHz are achievable.

• 3.3V operation for low power consumption and easy

integration into low-voltage systems

• 5V-tolerant inputs V_{IH max}= 5V

• Fully asynchronous and simultaneous read and write

operation

• Empty, Full, and Programmable Almost Empty and

Almost Full status flags

• TTL compatible

• Output Enable (OE) pin

Depth expansion is possible using one enable input for system

control, while the other enable is controlled by expansion logic

to direct the flow of data.

• Independent read and write enable pins

• Center power and ground pins for reduced noise

• Width expansion capability

Pin Configuration

Logic Block Diagram

0− 8

PLCC

Top View

INPUT

1 323130

PAF

PAE

GND

REN1

RCLK

REN2

WEN1

27 WCLK

WCLKWEN1 WEN2/LD

WEN2/LD

FLAG

PROGRAM

WRITE

CONTROL

14151617181920

PAE

PAF

FLAG

LOGIC

Dual Port

RAM Array

64 x 9

WRITE

POINTER

READ

POINTER

8Kx 9

RESET

LOGIC

THREE-STATE

OUTPUTREGISTER

READ

CONTROL

0− 8

RCLK REN1 REN2

Cypress Semiconductor Corporation

Document #: 38-06010 Rev. *B

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised July 14, 2005

12 3 4 5 6 7...18

中文翻译

下载PDF

与CY7C4211V-15AI相关器件

型号	品牌	获取价格	描述	数据表
CY7C4211V-15AIT	ROCHESTER	获取价格	IC,FIFO,512X9,SYNCHRONOUS,CMOS,TQFP,32PIN,PLASTIC
CY7C4211V-15AXI	CYPRESS	获取价格	Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
CY7C4211V-15JC	CYPRESS	获取价格	Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
CY7C4211V-15JCT	CYPRESS	获取价格	FIFO, 512X9, 11ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C4211V-25AC	CYPRESS	获取价格	Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
CY7C4211V-25JC	CYPRESS	获取价格	Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
CY7C4211V-25JCR	CYPRESS	获取价格	FIFO, 512X9, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C4211V-25JCT	CYPRESS	获取价格	FIFO, 512X9, 15ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C4211V-35AC	CYPRESS	获取价格	FIFO, 512X9, 20ns, Synchronous, CMOS, PQFP32, 7 X 7 MM, 1 MM HEIGHT, PLASTIC, TQFP-32
CY7C4211V-35JC	CYPRESS	获取价格	FIFO, 512X9, 20ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32

与CY7C4211V-15AI相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

17
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

12
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

42
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

36

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C4211V-15AI

CY7C4211V-15AI 数据手册

与CY7C4211V-15AI相关器件

与CY7C4211V-15AI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C4211V-15AI

CY7C4211V-15AI 数据手册

与CY7C4211V-15AI相关器件

与CY7C4211V-15AI相关文章

您还可以找

您在本页遇到什么问题？