Datasheet > 存储 > FIFO> CY7C421-25VIR

CY7C421-25VIR

更新时间： 2024-11-09 13:07:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片
页数	文件大小	规格书
22页	512K
描述
FIFO, 512X9, 25ns, Asynchronous, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

CY7C421-25VIR 技术参数

生命周期：	Obsolete	零件包装代码：	SOJ
包装说明：	SOJ,	针数：	28
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.7
Is Samacsys：	N	最长访问时间：	25 ns
其他特性：	RETRANSMIT	周期时间：	35 ns
JESD-30 代码：	R-PDSO-J28	长度：	17.91 mm
内存密度：	4608 bit	内存宽度：	9
功能数量：	1	端子数量：	28
字数：	512 words	字数代码：	512
工作模式：	ASYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	512X9
输出特性：	3-STATE	可输出：	NO
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOJ
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
并行/串行：	PARALLEL	认证状态：	Not Qualified
座面最大高度：	3.56 mm	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	7.5 mm	Base Number Matches：	1

CY7C421-25VIR 数据手册

19/21/25/29/

CY7C419/21/25/29/33

256/512/1K/2K/4K x 9 Asynchronous FIFO

Each FIFO memory is organized such that the data is read in

the same sequential order that it was written. Full and Empty

Features

• Asynchronous first-in first-out (FIFO) buffer memories

• 256 x 9 (CY7C419)

• 512 x 9 (CY7C421)

• 1K x 9 (CY7C425)

• 2K x 9 (CY7C429)

flags are provided to prevent overrun and underrun. Three ad-

ditional pins are also provided to facilitate unlimited expansion

in width, depth, or both. The depth expansion technique steers

the control signals from one device to another in parallel, thus

eliminating the serial addition of propagation delays, so that

throughput is not reduced. Data is steered in a similar manner.

• 4K x 9 (CY7C433)

• Dual-ported RAM cell

• High-speed 50.0-MHz read/write independent of

depth/width

• Low operating power: I_CC= 35 mA

• Empty and Full flags (Half Full flag in standalone)

• TTL compatible

• Retransmit in standalone

• Expandable in width

• PLCC, 7x7 TQFP, SOJ, 300-mil and 600-mil DIP

The read and write operations may be asynchronous; each

can occur at a rate of 50.0 MHz. The write operation occurs

when the write (W) signal is LOW. Read occurs when read (R)

goes LOW. The nine data outputs go to the high-impedance

state when R is HIGH.

A Half Full (HF) output flag is provided that is valid in the stan-

dalone and width expansion configurations. In the depth ex-

pansion configuration, this pin provides the expansion out

(XO) information that is used to tell the next FIFO that it will be

activated.

In the standalone and width expansion configurations, a LOW

on the retransmit (RT) input causes the FIFOs to retransmit

the data. Read enable (R) and write enable (W) must both be

HIGH during retransmit, and then R is used to access the data.

• Pin compatible and functionally equivalent to IDT7200,

IDT7201, IDT7202, IDT7203, IDT7204, AM7200, AM7201,

AM7202, AM7203, and AM7204

Functional Description

The CY7C419, CY7C420, CY7C421, CY7C424, CY7C425,

CY7C428, CY7C429, CY7C432, and CY7C433 are fabricated

using an advanced 0.65-micron P-well CMOS technology. In-

put ESD protection is greater than 2000V and latch-up is pre-

vented by careful layout and guard rings.

The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9, and

CY7C432/3 are first-in first-out (FIFO) memories offered in

600-mil wide and 300-mil wide packages. They are, respec-

tively, 256, 512, 1,024, 2,048, and 4,096 words by 9-bits wide.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-06001 Rev. *A

Revised December 30, 2002

12 3 4 5 6 7...22

中文翻译

下载PDF

与CY7C421-25VIR相关器件

型号	品牌	获取价格	描述	数据表
CY7C421-25VIT	CYPRESS	获取价格	FIFO, 512X9, 25ns, Asynchronous, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28
CY7C421-30AC	CYPRESS	获取价格	FIFO, 512X9, 30ns, Asynchronous, CMOS, PQFP32, PLASTIC, TQFP-32
CY7C421-30AC	ROCHESTER	获取价格	512X9 OTHER FIFO, 30ns, PQFP32, PLASTIC, TQFP-32
CY7C421-30DC	ETC	获取价格	x9 Asynchronous FIFO
CY7C421-30DI	ETC	获取价格	x9 Asynchronous FIFO
CY7C421-30DMB	CYPRESS	获取价格	256/512/1K/2K/4K x 9 Asynchronous FIFO
CY7C421-30JC	CYPRESS	获取价格	256/512/1K/2K/4K x 9 Asynchronous FIFO
CY7C421-30JCR	CYPRESS	获取价格	FIFO, 512X9, 30ns, Asynchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C421-30JCT	CYPRESS	获取价格	FIFO, 512X9, 30ns, Asynchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C421-30JI	CYPRESS	获取价格	256/512/1K/2K/4K x 9 Asynchronous FIFO

与CY7C421-25VIR相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

22
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

21
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

47
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

39

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C421-25VIR

CY7C421-25VIR 技术参数

CY7C421-25VIR 数据手册

与CY7C421-25VIR相关器件

与CY7C421-25VIR相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C421-25VIR

CY7C421-25VIR 技术参数

CY7C421-25VIR 数据手册

与CY7C421-25VIR相关器件

与CY7C421-25VIR相关文章

您还可以找

您在本页遇到什么问题？