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CY7C276-35HC PDF预览

CY7C276-35HC

更新时间: 2024-01-21 20:00:58
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路可编程只读存储器电动程控只读存储器
页数 文件大小 规格书
9页 138K
描述
16K x 16 Reprogrammable PROM

CY7C276-35HC 技术参数

生命周期:Obsolete零件包装代码:LCC
包装说明:WQCCN, LCC44,.65SQ针数:44
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.61风险等级:5.82
Is Samacsys:N最长访问时间:35 ns
I/O 类型:COMMONJESD-30 代码:S-CQCC-N44
长度:16.51 mm内存密度:262144 bit
内存集成电路类型:UVPROM内存宽度:16
功能数量:1端子数量:44
字数:16384 words字数代码:16000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:16KX16
输出特性:3-STATE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:WQCCN封装等效代码:LCC44,.65SQ
封装形状:SQUARE封装形式:CHIP CARRIER, WINDOW
并行/串行:PARALLEL电源:5 V
认证状态:Not Qualified筛选级别:MIL-STD-883
座面最大高度:2.794 mm最大待机电流:0.2 A
子类别:EPROMs最大压摆率:0.2 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD宽度:16.51 mm
Base Number Matches:1

CY7C276-35HC 数据手册

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1CY7C276  
CY7C276  
16K x 16 Reprogrammable PROM  
Functional Description  
Features  
The CY7C276 is a high-performance 16K-word by 16-bit  
CMOS PROM. It is available in a 44-pin PLCC/CLCC and a  
44-pin LCC packages, and is 100% reprogrammable in win-  
dowed packages. The memory cells utilize proven EPROM  
floating gate technology and word-wide programming algo-  
rithms.  
0.8-micron CMOS for optimum speed/power  
High speed (for commercial and military)  
25-ns access time  
16-bit-wide words  
Three programmable chip selects  
Programmable output enable  
44-pin PLCC and 44-pin LCC packages  
100% reprogrammable in windowed packages  
TTL-compatible I/O  
The CY7C276 allows the user to independently program the  
polarity of each chip select (CS CS ). This provides on-chip  
2
0
decoding of up to eight banks of PROM. The polarity of the  
asynchronous output enable pin (OE) is also programmable.  
In order to read the CY7C276, all three chip selects must be  
active and OE must be asserted. The contents of the memory  
location addressed by the address lines (A A ) will become  
13  
0
Capable of withstanding greater than 2001V static dis-  
charge  
available on the output lines (D D ). The data will remain on  
15  
0
the outputs until the address changes or the outputs are dis-  
abled.  
Logic Block Diagram  
Pin Configuration  
LCC/PLCC/CLCC  
D
D
A
15  
13  
Top View  
A
12  
A
11  
A
10  
16K x 16  
PROGRAMMABLE  
ARRAY  
14  
D
D
D
D
13  
A
9
A
8
12  
6
5
4
3
2
1
44 43 42 41 40  
39  
A
7
D
D
A
13  
A
12  
A
11  
12  
7
11  
A
6
11  
8
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
D
10  
9
A
5
10  
D
D
9
A
A
V
10  
11  
12  
13  
14  
15  
16  
17  
10  
A
A
4
8
9
D
9
8
7
6
V
SS  
3
SS  
V
CC  
V
SS  
A
2
D
D
7
A
8
A
1
D
D
A
7
6
D
A
5
4
A
6
0
D
A
5
D
18 19 20 21 22 23 24 25 26 27 28  
D
5
4
3
2
D
D
CS  
0
C276–2  
D
CS  
DECODE  
CS  
CS  
1
2
D
1
D
0
C276–1  
OE  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
March 1991 – Revised December 1993  

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