CY7C276-35JCR

更新时间： 2024-02-08 01:48:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路可编程只读存储器电动程控只读存储器
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CY7C276-35JCR 数据手册

1CY7C276

CY7C276

16K x 16 Reprogrammable PROM

Functional Description

Features

The CY7C276 is a high-performance 16K-word by 16-bit

CMOS PROM. It is available in a 44-pin PLCC/CLCC and a

44-pin LCC packages, and is 100% reprogrammable in win-

dowed packages. The memory cells utilize proven EPROM

floating gate technology and word-wide programming algo-

rithms.

•

0.8-micron CMOS for optimum speed/power

High speed (for commercial and military)

— 25-ns access time

•

16-bit-wide words

Three programmable chip selects

Programmable output enable

44-pin PLCC and 44-pin LCC packages

100% reprogrammable in windowed packages

TTL-compatible I/O

The CY7C276 allows the user to independently program the

polarity of each chip select (CS −CS ). This provides on-chip

decoding of up to eight banks of PROM. The polarity of the

asynchronous output enable pin (OE) is also programmable.

In order to read the CY7C276, all three chip selects must be

active and OE must be asserted. The contents of the memory

location addressed by the address lines (A −A ) will become

Capable of withstanding greater than 2001V static dis-

charge

available on the output lines (D −D ). The data will remain on

the outputs until the address changes or the outputs are dis-

abled.

Logic Block Diagram

Pin Configuration

LCC/PLCC/CLCC

Top View

16K x 16

PROGRAMMABLE

ARRAY

44 43 42 41 40

18 19 20 21 22 23 24 25 26 27 28

C276–2

DECODE

C276–1

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

March 1991 – Revised December 1993

12 3 4 5 6 7...9

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