Datasheet > CY7C2644KV18

CY7C2644KV18

更新时间： 2022-04-16 11:28:59

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
30页	840K
描述
144-Mbit QDRÂ® II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT

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CY7C2644KV18 数据手册

CY7C2644KV18

144-Mbit QDR^®II+ SRAM Two-Word Burst

Architecture(2.0CycleReadLatency)withODT

144-Mbit QDR^®II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT

Features

Configurations

■ Separate independent read and write data ports

❐ Supports concurrent transactions

With Read Cycle Latency of 2.0 cycles:

CY7C2644KV18 – 4 M × 36

■ 333-MHz clock for high bandwidth

Functional Description

■ Two-word burst for reducing address bus frequency

The CY7C2644KV18 is 1.8-V synchronous pipelined SRAM,

equipped with QDR^®II+ architecture. Similar to QDR II

architecture, QDR II+ architecture consists of two separate

ports: the read port and the write port to access the memory

array. The read port has dedicated data outputs to support read

operations and the write port has dedicated data inputs to

support write operations. QDR II+ architecture has separate data

inputs and data outputs to completely eliminate the need to “turn

around” the data bus that exists with common I/O devices.

Access to each port is through a common address bus.

Addresses for read and write addresses are latched on alternate

rising edges of the input (K) clock. Accesses to the QDR II+ read

and write ports are completely independent of one another. To

maximize data throughput, both read and write ports are

equipped with DDR interfaces. Each address location is

associated with two 36-bit words (CY7C2644KV18) that burst

sequentially into or out of the device. Because data can be

transferred into and out of the device on every rising edge of both

input clocks (K and K), memory bandwidth is maximized while

simplifying system design by eliminating bus “turn arounds”.

■ Double data rate (DDR) interfaces on both read and write ports

(data transferred at 666 MHz) at 333 MHz

■ Available in 2.0-clock cycle latency

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ On-die termination (ODT) feature

❐ Supported for D_[x:0], BWS_[x:0], and K/K inputs

■ Single multiplexed address input bus latches address inputs

for both read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ Quad data rate (QDR^®) II+ operates with 2.0-cycle read latency

when DOFF is asserted high

These devices have an ODT feature supported for D_[x:0]

■ Operates similar to QDR I device with one cycle read latency

when DOFF is asserted low

BWS_[x:0], and K/K inputs, which helps eliminate external

termination resistors, reduce cost, reduce board area, and

simplify board routing.

■ Available in × 36 configuration

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

■ Full data coherency, providing most current data

[1]

■ Core V_DD= 1.8 V± 0.1 V; I/O V_DDQ= 1.4 V to V_DD

❐ Supports both 1.5 V and 1.8 V I/O supply

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ High-speed transceiver logic (HSTL) inputs and variable drive

HSTL output buffers

■ Available in 165-ball fine pitch ball grid array (FBGA) package

(15 × 17 × 1.4 mm)

■ Offered in non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Phase Locked Loop (PLL) for accurate data placement

Selection Guide

Description

Maximum operating frequency

Maximum operating current

333 MHz

333

1160

300 MHz Unit

300

MHz

× 36

1080

Note

1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V

= 1.4 V to V

DDQ

Cypress Semiconductor Corporation

Document Number: 001-44138 Rev. *I

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised November 2, 2012

12 3 4 5 6 7...30

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与CY7C2644KV18相关器件

型号	品牌	获取价格	描述	数据表
CY7C2644KV18-300BZI	CYPRESS	获取价格	144-Mbit QDRÂ® II SRAM Two-Word Burst Archite
CY7C2644KV18-300BZXI	CYPRESS	获取价格	QDR SRAM, 4MX36, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
CY7C2644KV18-333BZI	CYPRESS	获取价格	144-Mbit QDRÂ® II SRAM Two-Word Burst Archite
CY7C2644KV18-333BZXI	CYPRESS	获取价格	QDR SRAM, 8MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBG
CY7C264-55DC	CYPRESS	获取价格	8K x 8 Power-Switched and Reprogrammable PROM
CY7C264-55DI	CYPRESS	获取价格	OTP ROM, 8KX8, 55ns, CMOS, CDIP24, 0.600 INCH, CERDIP-24
CY7C264-55DMB	CYPRESS	获取价格	8K x 8 Power-Switched and Reprogrammable PROM
CY7C264-55PC	CYPRESS	获取价格	8K x 8 Power-Switched and Reprogrammable PROM
CY7C264-55PI	CYPRESS	获取价格	OTP ROM, 8KX8, 55ns, CMOS, PDIP24, 0.600 INCH, PLASTIC, DIP-24
CY7C264-55WC	CYPRESS	获取价格	8K x 8 Power-Switched and Reprogrammable PROM

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