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CY7C265_06 PDF预览

CY7C265_06

更新时间: 2022-04-23 23:00:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 可编程只读存储器
页数 文件大小 规格书
13页 456K
描述
8K x 8 Registered PROM

CY7C265_06 数据手册

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CY7C265  
8K x 8 Registered PROM  
are enabled. One pin on the CY7C265 is programmed to  
perform either the enable or the initialize function.  
Features  
• CMOS for optimum speed/power  
• High speed (Commercial)  
If the asynchronous enable (E) is being used, the outputs may  
be disabled at any time by switching the enable to a logic  
HIGH, and may be returned to the active state by switching the  
enable to a logic LOW.  
— 15 ns address set-up  
— 12 ns clock to output  
If the synchronous enable (ES) is being used, the outputs will  
go to the OFF or high-impedance state upon the next positive  
clock edge after the synchronous enable input is switched to  
a HIGH level. If the synchronous enable pin is switched to a  
logic LOW, the subsequent positive clock edge will return the  
output to the active state. Following a positive clock edge, the  
address and synchronous enable inputs are free to change  
since no change in the output will occur until the next  
LOW-to-HIGH transition of the clock. This unique feature al-  
lows the CY7C265 decoders and sense amplifiers to access  
the next location while previously addressed data remains sta-  
ble on the outputs.  
• Low power  
— 660 mW (Commercial)  
• On-chip edge-triggered registers  
— Ideal for pipelined microprogrammed systems  
• EPROM technology  
— 100% programmable  
— Reprogrammable (CY7C265W)  
5V ±10% VCC, commercial and military  
• Capable of withstanding >2001V static discharge  
• Slim 28-pin, 300-mil plastic or hermetic DIP  
If the E/I pin is used for INIT (asynchronous), then the outputs  
are permanently enabled. The initialize function is useful  
during power-up and time-out sequences, and can facilitate  
implementation of other sophisticated functions such as a  
built-in “jump start” address. When activated, the initialize  
control input causes the contents of a user programmed  
8193rd 8-bit word to be loaded into the on-chip register. Each  
bit is programmable and the initialize function can be used to  
load any desired combination of 1’s and 0’s into the register.  
In the unprogrammed state, activating INIT will generate a  
register clear (all outputs LOW). If all the bits of the initialize  
word are programmed to be a 1, activating INIT performs a  
register preset (all outputs HIGH).  
Functional Description  
The CY7C265 is a 8192 x 8 registered PROM. It is organized  
as 8,192 words by 8 bits wide, and has a pipeline output  
register. In addition, the device features a programmable  
initialize byte that may be loaded into the pipeline register with  
the initialize signal. The programmable initialize byte is the  
8,193rd byte in the PROM and its value is programmed at the  
time of use.  
Packaged in 28 pins, the PROM has 13 address signals (A0  
through A12), 8 data out signals (O0 through O7), E/I (enable  
or initialize), and CLOCK.  
Applying a LOW to the INIT input causes an immediate load  
of the programmed initialize word into the pipeline register and  
onto the outputs. The INIT LOW disables clock and must  
return HIGH to enable clock independent of all other inputs,  
including the clock.  
CLOCK functions as a pipeline clock, loading the contents of  
the addressed memory location into the pipeline register on  
each rising edge. The data will appear on the outputs if they  
Cypress Semiconductor Corporation  
Document #: 38-04012 Rev. *B  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised August 17, 2006  
[+] Feedback  

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