CY7C245A
2K x 8 Reprogrammable Registered PROM
Features
Functional Description
The CY7C245A is a high-performance, 2K x 8, electrically
programmable, read-only memory packaged in a slim 300-mil
plastic or hermetic DIP. The ceramic package may be
equipped with an erasure window; when exposed to UV light
the PROM is erased and can then be reprogrammed. The
memory cells utilize proven EPROM floating-gate technology
and byte-wide intelligent programming algorithms.
• Windowed for reprogrammability
• CMOS for optimum speed/power
• High speed
— 15-ns address set-up
— 10-ns clock to output
• Low power
The CY7C245A replaces bipolar devices and offers the advan-
tages of lower power, reprogrammability, superior perfor-
mance and high programming yield. The EPROM cell requires
only 12.5V for the supervoltage, and low current requirements
— 330 mW (commercial) for -25 ns
— 660 mW (military)
allow gang programming. The EPROM cells allow each
memory location to be tested 100%, because each location is
written into, erased, and repeatedly exercised prior to encap-
sulation. Each PROM is also tested for AC performance to
guarantee that after customer programming the product will
meet AC specification limits.
• Programmable synchronous or asynchronous output
enable
• On-chip edge-triggered registers
• Programmable asynchronous register (INIT)
• EPROM technology, 100% programmable
• Slim, 300-mil, 24-pin plastic or hermetic DIP
• 5V 10% VCC, commercial and military
• TTL-compatible I/O
The CY7C245A has an asynchronous initialize function (INIT).
This function acts as a 2049th 8-bit word loaded into the
on-chip register. It is user programmable with any desired
word, or may be used as a PRESET or CLEAR function on the
outputs. INIT is triggered by a low level, not an edge.
• Direct replacement for bipolar PROMs
• Capable of withstanding greater than 2001V static
discharge
Logic Block Diagram
Pin Configurations
DIP Top View
INIT
1
24
23
22
21
20
19
18
17
16
A
A
6
V
CC
O
7
A
0
2
3
4
A
8
7
O
A
1
A
A
5
9
A
2
A
4
A
10
PROGRAMMABLE
ARRAY
ROW
6
O
MULTIPLEXER
5
A
A
3
ADDRESS
3
INIT
E/E
S
A
6
2
A
4
8-BIT
A
1
5
O
7
8
9
CP
EDGE-
A
5
TRIGGERED
REGISTER
A
0
O
7
ADDRESS
DECODER
A
6
4
O
0
O
6
O
O
10
11
12
O
5
A
1
15
14
13
7
O
O
4
2
3
O
A
8
GND
O
3
A
9
COLUMN
LCC/PLCC (Opaque only) Top View
2
O
ADDRESS
A
10
1
O
3 2 1 2827
26
4
CP
A
25 10
A
5
4
3
PROGRAMMABLE
MULTIPLEXER
A
24
23
22
21
20
19
INIT
6
0
A
E/E
D
C
Q
2
E/E
S
S
7
A
1
CP
NC
8
A
0
9
CP
NC
O
7
10
11
O
0
O
6
131415161718
12
Selection Guide
7C245A-15
7C245A-18
7C245A-25
7C245A-35
Unit
ns
Minimum Address Set-up Time
Maximum Clock to Output
15
10
18
12
25
12
35
15
ns
Maximum Operating Current Standard Commercial
Military
120
120
120
90
90
mA
mA
120
120
Cypress Semiconductor Corporation
Document #: 38-04007 Rev. *D
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
RevisedNovember4, 2003