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CY7C235A-40DMB PDF预览

CY7C235A-40DMB

更新时间： 2024-11-23 21:58:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 可编程只读存储器
页数 文件大小 规格书
10页 214K
描述
1K x 8 Registered PROM

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CY7C235A-40DMB 数据手册

 浏览型号CY7C235A-40DMB的Datasheet PDF文件第2页浏览型号CY7C235A-40DMB的Datasheet PDF文件第3页浏览型号CY7C235A-40DMB的Datasheet PDF文件第4页浏览型号CY7C235A-40DMB的Datasheet PDF文件第5页浏览型号CY7C235A-40DMB的Datasheet PDF文件第6页浏览型号CY7C235A-40DMB的Datasheet PDF文件第7页 
1CY7C235A  
CY7C235A  
1K x 8 Registered PROM  
• Capable of withstanding greater than 2001V static  
discharge  
Features  
• CMOS for optimum speed/power  
• High speed  
Functional Description  
— 25 ns address set-up  
The CY7C235A is a high-performance 1024-word by 8-bit  
electrically programmable read only memory packaged in a  
slim 300-mil plastic or hermetic DIP, 28-pin leadless chip  
carrier, or 28-pin plastic leaded chip carrier. The memory cells  
utilize proven EPROM floating gate technology and byte-wide  
intelligent programming algorithms.  
— 12 ns clock to output  
• Low power  
— 495 mW (Commercial)  
— 660 mW (Military)  
The CY7C235A replaces bipolar devices pin for pin and offers  
the advantages of lower power, superior performance, and  
high programming yield. The EPROM cell requires only 12.5V  
for the supervoltage, and low current requirements allow for  
gang programming. The EPROM cells allow for each memory  
location to be tested 100%, as each location is written into,  
erased, and repeatedly exercised prior to encapsulation. Each  
PROM is also tested for AC performance to guarantee that the  
product will meet AC specification limits after customer  
programming.  
• Synchronous and asynchronous output enables  
• On-chip edge-triggered registers  
• Programmable asynchronous registers (INIT)  
• EPROM technology, 100% programmable  
• Slim, 300-mil, 24-pin plastic or hermetic DIP or 28-pin  
LCC and PLCC  
• 5V ±10% VCC, commercial and military  
• TTL-compatible I/O  
• Direct replacement for bipolar PROMs  
Logic Block Diagram  
Pin Configuration  
DIP  
Top View  
INIT  
1
24  
23  
22  
21  
V
A
A
6
CC  
7
2
3
O
7
A
8
A
9
A
5
4
A
9
A
4
E
INIT  
E
S
O
6
5
6
A
20  
19  
18  
17  
16  
3
A
PROGRAMMABLE  
ARRAY  
8
ROW  
ADDRESS  
MULTIPLEXER  
A
2
A
7
A
1
O
5
7
8
9
CP  
O
7
O
6
A
0
8-BIT  
A
6
EDGE-  
O
0
O
4
A
5
TRIGGERED  
REGISTER  
ADDRESS  
DECODER  
O
1
10  
11  
12  
O
5
15  
14  
13  
O
GND  
O
4
A
4
2
O
3
O
3
A
3
A
2
O
2
COLUMN  
ADDRESS  
LCC/PLCC  
Top View  
A
1
O
1
A
0
O
0
CP  
3 2 1 2827  
4
26  
E
25  
24  
23  
22  
21  
20  
19  
A
4
5
CP  
INIT  
A
3
6
E
A
S
2
7
CP  
NC  
A
1
8
A
0
9
E
S
NC  
O
7
O
6
10  
O
0
11  
131415161718  
12  
E
Selection Guide  
7C235A-25  
7C235A-30  
7C235A-40  
Unit  
ns  
Minimum Address Set-Up Time  
Maximum Clock to Output  
25  
12  
90  
30  
15  
90  
40  
20  
ns  
Maximum Operating  
Current  
Commercial  
Military  
90  
mA  
mA  
120  
Cypress Semiconductor Corporation  
Document #: 38-04002 Rev. *B  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Revised December 27, 2002  
1234567...10

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