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CY7C2265KV18-550BZXC PDF预览

CY7C2265KV18-550BZXC

更新时间： 2024-01-16 03:07:29
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
32页 660K
描述
QDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165

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CY7C2265KV18-550BZXC 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：LBGA, BGA165,11X15,40Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
Factory Lead Time：1 week风险等级：2.33
最长访问时间：0.45 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：550 MHzI/O 类型：SEPARATE
JESD-30 代码：R-PBGA-B165JESD-609代码：e1
长度：15 mm内存密度：37748736 bit
内存集成电路类型：QDR SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端子数量：165字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：1MX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：1.5/1.8,1.8 V
认证状态：Not Qualified座面最大高度：1.4 mm
最大待机电流：0.36 A最小待机电流：1.7 V
子类别：SRAMs最大压摆率：1.21 mA
最大供电电压 (Vsup)：1.9 V最小供电电压 (Vsup)：1.7 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：13 mm
Base Number Matches：1

CY7C2265KV18-550BZXC 数据手册

 浏览型号CY7C2265KV18-550BZXC的Datasheet PDF文件第2页浏览型号CY7C2265KV18-550BZXC的Datasheet PDF文件第3页浏览型号CY7C2265KV18-550BZXC的Datasheet PDF文件第4页浏览型号CY7C2265KV18-550BZXC的Datasheet PDF文件第6页浏览型号CY7C2265KV18-550BZXC的Datasheet PDF文件第7页浏览型号CY7C2265KV18-550BZXC的Datasheet PDF文件第8页 
CY7C2263KV18/CY7C2265KV18  
Pin Definitions  
Pin Name  
I/O  
Pin Description  
Data input signals. Sampled on the rising edge of K and K clocks when valid write operations are active.  
D[x:0]  
Input-  
synchronous CY7C2263KV18 D[17:0]  
CY7C2265KV18 D[35:0]  
WPS  
Input-  
Write port select active LOW. Sampled on the rising edge of the K clock. When asserted active, a  
synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0]  
.
BWS0,  
BWS1,  
BWS2,  
BWS3  
Input-  
Byte write select 0, 1, 2 and 3 active LOW. Sampled on the rising edge of the K and K clocks when  
synchronous write operations are active. Used to select which byte is written into the device during the current portion  
of the write operations. Bytes not written remain unaltered.  
CY7C2263KV18 BWS0 controls D[8:0] and BWS1 controls D[17:9].  
CY7C2265KV18 BWS0 controls D[8:0], BWS1 controls D[17:9]  
,
BWS2 controls D[26:18] and BWS3 controls D[35:27].  
All the byte write selects are sampled on the same edge as the data. Deselecting a byte write select  
ignores the corresponding byte of data and it is not written into the device  
.
A
Input-  
Address inputs. Sampled on the rising edge of the K clock during active read and write operations.  
synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is  
organized as 2 M × 18 (4 arrays each of 512 K × 18) for CY7C2263KV18 and 1 M × 36 (4 arrays each  
of 256 K × 36) for CY7C2265KV18. Therefore, only 19 address inputs for CY7C2263KV18 and 18  
address inputs for CY7C2265KV18. These inputs are ignored when the appropriate port is deselected.  
Q[x:0]  
Outputs-  
Data output signals. These pins drive out the requested data when the read operation is active. Valid  
synchronous data is driven out on the rising edge of the K and K clocks during read operations. On deselecting the  
read port, Q[x:0] are automatically tri-stated.  
CY7C2263KV18 Q[17:0]  
CY7C2265KV18 Q[35:0]  
RPS  
Input-  
Read port select active LOW. Sampled on the rising edge of positive input clock (K). When active, a  
synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access  
is allowed to complete and the output drivers are automatically tristated following the next rising edge of  
the K clock. Each read access consists of a burst of four sequential transfers.  
QVLD  
Valid output Valid output indicator. The Q valid indicates valid output data. QVLD is edge aligned with CQ and CQ.  
indicator  
ODT [3]  
On-die  
On-die termination input. This pin is used for on-die termination of the input signals. ODT range  
termination selection is made during power up initialization. A LOW on this pin selects a low range that follows  
input pin  
RQ/3.33 for 175 < RQ < 350 (where RQ is the resistor tied to ZQ pin)A HIGH on this pin selects a  
high range that follows RQ/1.66 for 175 < RQ < 250 (where RQ is the resistor tied to ZQ pin). When  
left floating, a high range termination value is selected by default.  
K
Input clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device  
and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.  
K
Input clock Negative input clock input. K is used to capture synchronous inputs being presented to the device and  
to drive out data through Q[x:0]  
.
CQ  
CQ  
ZQ  
Echo clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock  
(K) of the QDR II+. The timings for the echo clocks are shown in the Switching Characteristics on page 24.  
Echo clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock  
(K) of the QDR II+.The timings for the echo clocks are shown in the Switching Characteristics on page 24.  
Input  
Output impedance matching input. This input is used to tune the device outputs to the system data  
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor  
connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which  
enables the minimum impedance mode. This pin cannot be connected directly to GND or left  
unconnected.  
Note  
3. On-die termination (ODT) feature is supported for D  
, BWS  
, and K/K inputs.  
[x:0]  
[x:0]  
Document Number: 001-57843 Rev. *L  
Page 5 of 32  
 
 
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