CY7C2263XV18
CY7C2265XV18
Pin Definitions
Pin Name
I/O
Pin Description
Data Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active.
D[x:0]
Input-
Synchronous CY7C2263XV18 D[17:0]
CY7C2265XV18 D[35:0]
WPS
Input-
Write Port Select Active LOW. Sampled on the rising edge of the K clock. When asserted active, a
Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0]
.
BWS0,
BWS1,
BWS2,
BWS3
Input-
Byte Write Select 0, 1, 2 and 3 Active LOW. Sampled on the rising edge of the K and K clocks when
Synchronous write operations are active. Used to select which byte is written into the device during the current portion
of the write operations. Bytes not written remain unaltered.
CY7C2263XV18 BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C2265XV18 BWS0 controls D[8:0], BWS1 controls D[17:9]
,
BWS2 controls D[26:18] and BWS3 controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device
.
A
Input-
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations.
Synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 2 M × 18 (4 arrays each of 512 K × 18) for CY7C2263XV18 and 1 M × 36 (4 arrays each
of 256 K × 36) for CY7C2265XV18. Therefore, only 19 address inputs for CY7C2263XV18 and 18
address inputs for CY7C2265XV18. These inputs are ignored when the appropriate port is deselected.
The address pins (A) can be assigned any bit order.
Q[x:0]
Outputs-
Data Output Signals. These pins drive out the requested data when the read operation is active. Valid
Synchronous data is driven out on the rising edge of the K and K clocks during read operations. On deselecting the
read port, Q[x:0] are automatically tri-stated.
CY7C2263XV18 Q[17:0]
CY7C2265XV18 Q[35:0]
RPS
Input-
Read Port Select Active LOW. Sampled on the rising edge of positive input clock (K). When active,
Synchronous a read operation is initiated. Deasserting deselects the read port. When deselected, the pending access
is allowed to complete and the output drivers are automatically tri-stated following the next rising edge
of the K clock. Each read access consists of a burst of four sequential transfers.
QVLD
Valid Output Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
Indicator
ODT [2]
On-Die
On-Die Termination Input. This pin is used for On-Die termination of the input signals. ODT range
Termination selection is made during power up initialization. A LOW on this pin selects a low range that follows
Input Pin
RQ/3.33 for 175 < RQ < 350 (where RQ is the resistor tied to ZQ pin)A HIGH on this pin selects a
high range that follows RQ/1.66 for 175 < RQ < 250 (where RQ is the resistor tied to ZQ pin). When
left floating, a high range termination value is selected by default.
K
Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.
K
Input Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device
and to drive out data through Q[x:0]
.
CQ
Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR II+ Xtreme.The timings for the echo clocks are shown in the Switching Characteristics
on page 23.
CQ
Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR II+ Xtreme.The timings for the echo clocks are shown in the Switching Characteristics
on page 23.
Note
2. On-Die Termination (ODT) feature is supported for D
, BWS
, and K/K inputs.
[x:0]
[x:0]
Document Number: 001-70331 Rev. *F
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