CY7C2262XV18, CY7C2264XV18
36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst
Architecture (2.5 Cycle Read Latency) with ODT
36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
Features
Configurations
■ Separate independent read and write data ports
❐ Supports concurrent transactions
With Read Cycle Latency of 2.5 cycles:
CY7C2262XV18 – 2 M × 18
■ 450 MHz clock for high bandwidth
CY7C2264XV18 – 1 M × 36
■ 2-word burst for reducing address bus frequency
Functional Description
■ DoubleDataRate(DDR)interfacesonbothreadandwriteports
(data transferred at 900 MHz) at 450 MHz
The CY7C2262XV18, and CY7C2264XV18 are 1.8 V
Synchronous Pipelined SRAMs, equipped with QDR™-II+
architecture. Similar to QDR II architecture, QDR II+ architecture
consists of two separate ports: the read port and the write port to
access the memory array. The read port has dedicated data
outputs to support read operations and the write port has
dedicated data inputs to support write operations. QDR II+
architecture has separate data inputs and data outputs to
completely eliminate the need to “turnaround” the data bus that
exists with common devices. Access to each port is through a
common address bus. Addresses for read and write addresses
are latched on alternate rising edges of the input (K) clock.
Accesses to the QDR II+ Xtreme read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with two 18-bit
words (CY7C2262XV18), or 36-bit words (CY7C2264XV18) that
burst sequentially into or out of the device. Because data can be
transferred into and out of the device on every rising edge of both
input clocks (K and K), memory bandwidth is maximized while
simplifying system design by eliminating bus “turnarounds”.
■ Available in 2.5 clock cycle latency
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ On-Die Termination (ODT) feature
❐ Supported for D[x:0], BWS[x:0], and K/K inputs
■ Single multiplexed address input bus latches address inputs
for both read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ QDR™-II+ Xtreme operates with 2.5 cycle read latency when
DOFF is asserted HIGH
These devices have an On-Die Termination feature supported
for D[x:0], BWS[x:0], and K/K inputs, which helps eliminate
external termination resistors, reduce cost, reduce board area,
and simplify board routing.
■ OperatessimilartoQDRIdevicewith1cyclereadlatencywhen
DOFF is asserted LOW
■ Available in × 18, and × 36 configurations
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
■ Full data coherency, providing most current data
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
■ Core VDD = 1.8 V ± 0.1 V; VDDQ = 1.4 V to 1.6 V
❐ Supports 1.5 V I/O supply
■ HSTL inputs and variable drive HSTL output buffers
■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
■ Offered in Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Phase Locked Loop (PLL) for accurate data placement
Selection Guide
Description
Maximum Operating Frequency
450 MHz
450
366 MHz Unit
366
970
MHz
mA
Maximum Operating Current
× 18
× 36
1205
1445
1165
Cypress Semiconductor Corporation
Document Number : 001-70330 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 25, 2012
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